From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Bernhard Beschow <shentey@gmail.com>, qemu-devel@nongnu.org
Cc: Jiaxun Yang <jiaxun.yang@flygoat.com>,
Huacai Chen <chenhuacai@kernel.org>
Subject: Re: [PATCH v2] hw/isa/vt82c686: Respect SCI interrupt assignment
Date: Wed, 4 Oct 2023 13:06:44 +0200 [thread overview]
Message-ID: <b9b3fbbf-c49b-6403-49d3-46b53e1f50d3@linaro.org> (raw)
In-Reply-To: <20231004105709.16994-1-shentey@gmail.com>
On 4/10/23 12:57, Bernhard Beschow wrote:
> According to the datasheet, SCI interrupts of the power management function
> aren't routed through the PCI pins but rather directly to the integrated PIC.
> The routing is configurable through the ACPI interrupt select register at offset
> 0x42 in the PCI configuration space of the ISA function.
>
> Signed-off-by: Bernhard Beschow <shentey@gmail.com>
>
> ---
>
> v2:
> * Introduce named constants for the ACPI interrupt select register at offset
> 0x42 (Phil)
> ---
> hw/isa/vt82c686.c | 47 +++++++++++++++++++++++++++++++++++------------
> 1 file changed, 35 insertions(+), 12 deletions(-)
Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org>
next prev parent reply other threads:[~2023-10-04 11:07 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-10-04 10:57 [PATCH v2] hw/isa/vt82c686: Respect SCI interrupt assignment Bernhard Beschow
2023-10-04 11:06 ` Philippe Mathieu-Daudé [this message]
2023-10-04 12:11 ` BALATON Zoltan
2023-10-04 12:28 ` BALATON Zoltan
2023-10-05 7:27 ` Bernhard Beschow
2023-10-05 11:26 ` BALATON Zoltan
2023-10-05 12:10 ` Bernhard Beschow
2023-10-05 12:38 ` BALATON Zoltan
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