From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 5FB50C8303D for ; Fri, 4 Jul 2025 03:35:06 +0000 (UTC) Received: from localhost ([::1] helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1uXXCM-00026S-7B; Thu, 03 Jul 2025 23:34:50 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uXXCK-000264-W2 for qemu-devel@nongnu.org; Thu, 03 Jul 2025 23:34:49 -0400 Received: from mgamail.intel.com ([198.175.65.14]) by eggs.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1uXXCJ-00035l-26 for qemu-devel@nongnu.org; Thu, 03 Jul 2025 23:34:48 -0400 DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1751600087; x=1783136087; h=message-id:date:mime-version:subject:to:cc:references: from:in-reply-to:content-transfer-encoding; bh=P6x2XPAWilpGvgkM5zWvBuCuPQkkZmW2VPmBJgqnXmc=; b=niayNkrRS+E+Ad7ltwNVwxIDO+X6nAWRuvCoGnUv8aRR7lu4IQL8vly9 Yvidly6jYO2X2s1IEXELAy1dG7MsTvDkwZ1oR5TJwqrtaHB13Spaod1DA xmpIzh1Z3oCzpGKBwgsOTgSMkH8JiILBO82KOkczfsPNduf8HEM1C6j++ uMxtuch9Zom+1QLA2V/QDLCnFuGSQNTnXEEApu6aKgNllbe9p3XK2Wde3 op6D9C4eSoRcHxT/QxRbzixESuWc7KqL0OrZUUL7P0ukJsDSLOnMygAme Y8W+JYjGp/SkBm/9uVvGubeKVnqduYiuSVEinKS/4z7mgcfaaQvTo7Tho A==; X-CSE-ConnectionGUID: n9yDOAb7Qei3iZ3gWarv/w== X-CSE-MsgGUID: nvajDPFMTCSiIzy4ifH5Fg== X-IronPort-AV: E=McAfee;i="6800,10657,11483"; a="57707765" X-IronPort-AV: E=Sophos;i="6.16,286,1744095600"; d="scan'208";a="57707765" Received: from orviesa005.jf.intel.com ([10.64.159.145]) by orvoesa106.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 20:34:45 -0700 X-CSE-ConnectionGUID: ELbnWY7CQHiKygKv32caWA== X-CSE-MsgGUID: KZ6MDGSvSkyD+M5b5D2hmg== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.16,286,1744095600"; d="scan'208";a="160223382" Received: from dapengmi-mobl1.ccr.corp.intel.com (HELO [10.124.240.37]) ([10.124.240.37]) by orviesa005-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Jul 2025 20:34:42 -0700 Message-ID: Date: Fri, 4 Jul 2025 11:34:39 +0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/8] i386/cpu: Introduce cache model for GraniteRapids To: Zhao Liu , Paolo Bonzini , =?UTF-8?Q?Daniel_P_=2E_Berrang=C3=A9?= , Igor Mammedov , Eduardo Habkost Cc: Ewan Hai , Jason Zeng , Xiaoyao Li , Tao Su , Yi Lai , Dapeng Mi , Tejus GK , Manish Mishra , qemu-devel@nongnu.org References: <20250626083105.2581859-1-zhao1.liu@intel.com> <20250626083105.2581859-3-zhao1.liu@intel.com> Content-Language: en-US From: "Mi, Dapeng" In-Reply-To: <20250626083105.2581859-3-zhao1.liu@intel.com> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Received-SPF: none client-ip=198.175.65.14; envelope-from=dapeng1.mi@linux.intel.com; helo=mgamail.intel.com X-Spam_score_int: -40 X-Spam_score: -4.1 X-Spam_bar: ---- X-Spam_report: (-4.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.237, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_NONE=0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/26/2025 4:30 PM, Zhao Liu wrote: > Add the cache model to GraniteRapids (v3) to better emulate its > environment. > > The cache model is based on GraniteRapids-SP (Scalable Performance): > > --- cache 0 --- > cache type = data cache (1) > cache level = 0x1 (1) > self-initializing cache level = true > fully associative cache = false > maximum IDs for CPUs sharing cache = 0x1 (1) > maximum IDs for cores in pkg = 0x3f (63) > system coherency line size = 0x40 (64) > physical line partitions = 0x1 (1) > ways of associativity = 0xc (12) > number of sets = 0x40 (64) > WBINVD/INVD acts on lower caches = false > inclusive to lower caches = false > complex cache indexing = false > number of sets (s) = 64 > (size synth) = 49152 (48 KB) > --- cache 1 --- > cache type = instruction cache (2) > cache level = 0x1 (1) > self-initializing cache level = true > fully associative cache = false > maximum IDs for CPUs sharing cache = 0x1 (1) > maximum IDs for cores in pkg = 0x3f (63) > system coherency line size = 0x40 (64) > physical line partitions = 0x1 (1) > ways of associativity = 0x10 (16) > number of sets = 0x40 (64) > WBINVD/INVD acts on lower caches = false > inclusive to lower caches = false > complex cache indexing = false > number of sets (s) = 64 > (size synth) = 65536 (64 KB) > --- cache 2 --- > cache type = unified cache (3) > cache level = 0x2 (2) > self-initializing cache level = true > fully associative cache = false > maximum IDs for CPUs sharing cache = 0x1 (1) > maximum IDs for cores in pkg = 0x3f (63) > system coherency line size = 0x40 (64) > physical line partitions = 0x1 (1) > ways of associativity = 0x10 (16) > number of sets = 0x800 (2048) > WBINVD/INVD acts on lower caches = false > inclusive to lower caches = false > complex cache indexing = false > number of sets (s) = 2048 > (size synth) = 2097152 (2 MB) > --- cache 3 --- > cache type = unified cache (3) > cache level = 0x3 (3) > self-initializing cache level = true > fully associative cache = false > maximum IDs for CPUs sharing cache = 0xff (255) > maximum IDs for cores in pkg = 0x3f (63) > system coherency line size = 0x40 (64) > physical line partitions = 0x1 (1) > ways of associativity = 0x10 (16) > number of sets = 0x48000 (294912) > WBINVD/INVD acts on lower caches = false > inclusive to lower caches = false > complex cache indexing = true > number of sets (s) = 294912 > (size synth) = 301989888 (288 MB) > --- cache 4 --- > cache type = no more caches (0) > > Suggested-by: Tejus GK > Suggested-by: Jason Zeng > Suggested-by: "Daniel P . Berrangé" > Signed-off-by: Zhao Liu > --- > target/i386/cpu.c | 96 +++++++++++++++++++++++++++++++++++++++++++++++ > 1 file changed, 96 insertions(+) > > diff --git a/target/i386/cpu.c b/target/i386/cpu.c > index fcaa2625b023..b40f1a5b6648 100644 > --- a/target/i386/cpu.c > +++ b/target/i386/cpu.c > @@ -2886,6 +2886,97 @@ static const CPUCaches epyc_turin_cache_info = { > } > }; > > +static const CPUCaches xeon_gnr_cache_info = { > + .l1d_cache = &(CPUCacheInfo) { > + /* CPUID 0x4.0x0.EAX */ > + .type = DATA_CACHE, > + .level = 1, > + .self_init = true, > + > + /* CPUID 0x4.0x0.EBX */ > + .line_size = 64, > + .partitions = 1, > + .associativity = 12, > + > + /* CPUID 0x4.0x0.ECX */ > + .sets = 64, > + > + /* CPUID 0x4.0x0.EDX */ > + .no_invd_sharing = false, > + .inclusive = false, > + .complex_indexing = false, > + > + .size = 48 * KiB, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l1i_cache = &(CPUCacheInfo) { > + /* CPUID 0x4.0x1.EAX */ > + .type = INSTRUCTION_CACHE, > + .level = 1, > + .self_init = true, > + > + /* CPUID 0x4.0x1.EBX */ > + .line_size = 64, > + .partitions = 1, > + .associativity = 16, > + > + /* CPUID 0x4.0x1.ECX */ > + .sets = 64, > + > + /* CPUID 0x4.0x1.EDX */ > + .no_invd_sharing = false, > + .inclusive = false, > + .complex_indexing = false, > + > + .size = 64 * KiB, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l2_cache = &(CPUCacheInfo) { > + /* CPUID 0x4.0x2.EAX */ > + .type = UNIFIED_CACHE, > + .level = 2, > + .self_init = true, > + > + /* CPUID 0x4.0x2.EBX */ > + .line_size = 64, > + .partitions = 1, > + .associativity = 16, > + > + /* CPUID 0x4.0x2.ECX */ > + .sets = 2048, > + > + /* CPUID 0x4.0x2.EDX */ > + .no_invd_sharing = false, > + .inclusive = false, > + .complex_indexing = false, > + > + .size = 2 * MiB, > + .share_level = CPU_TOPOLOGY_LEVEL_CORE, > + }, > + .l3_cache = &(CPUCacheInfo) { > + /* CPUID 0x4.0x3.EAX */ > + .type = UNIFIED_CACHE, > + .level = 3, > + .self_init = true, > + > + /* CPUID 0x4.0x3.EBX */ > + .line_size = 64, > + .partitions = 1, > + .associativity = 16, > + > + /* CPUID 0x4.0x3.ECX */ > + .sets = 294912, > + > + /* CPUID 0x4.0x3.EDX */ > + .no_invd_sharing = false, > + .inclusive = false, > + .complex_indexing = true, > + > + .size = 288 * MiB, > + .share_level = CPU_TOPOLOGY_LEVEL_SOCKET, > + }, > +}; > + > static const CPUCaches xeon_srf_cache_info = { > .l1d_cache = &(CPUCacheInfo) { > /* CPUID 0x4.0x0.EAX */ > @@ -4954,6 +5045,11 @@ static const X86CPUDefinition builtin_x86_defs[] = { > { /* end of list */ } > } > }, > + { > + .version = 3, > + .note = "with gnr-sp cache model", > + .cache_info = &xeon_gnr_cache_info, > + }, > { /* end of list */ }, > }, > }, Reviewed-by: Dapeng Mi