From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:37783) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1fufg4-0002p2-Jh for qemu-devel@nongnu.org; Tue, 28 Aug 2018 11:13:09 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1fufg1-0005fY-GL for qemu-devel@nongnu.org; Tue, 28 Aug 2018 11:13:08 -0400 Received: from smtp-fw-2101.amazon.com ([72.21.196.25]:53275) by eggs.gnu.org with esmtps (TLS1.0:RSA_ARCFOUR_SHA1:16) (Exim 4.71) (envelope-from ) id 1fufg1-0005fH-Bv for qemu-devel@nongnu.org; Tue, 28 Aug 2018 11:13:05 -0400 From: "Janeczek, Craig" Date: Tue, 28 Aug 2018 15:13:01 +0000 Message-ID: References: <20180828130041.26445-1-jancraig@amazon.com>, <20180828130041.26445-3-jancraig@amazon.com> In-Reply-To: Content-Language: en-US Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: quoted-printable MIME-Version: 1.0 Subject: Re: [Qemu-devel] [PATCH v3 2/8] target/mips: Add all MXU opcodes List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Aleksandar Markovic , "qemu-devel@nongnu.org" Cc: "aurelien@aurel32.net" I see that I can check the loongson instructions by checking for INSN_LOONG= SON2F. Using MXU if that is not set What should I check for the mult or misc instructions that were there first= ? -----Original Message----- From: Aleksandar Markovic =20 Sent: Tuesday, August 28, 2018 11:07 AM To: Janeczek, Craig ; qemu-devel@nongnu.org Cc: aurelien@aurel32.net Subject: Re: [PATCH v3 2/8] target/mips: Add all MXU opcodes > From: Craig Janeczek > Sent: Tuesday, August 28, 2018 3:00 PM > To: qemu-devel@nongnu.org > Cc: Aleksandar Markovic; aurelien@aurel32.net; Craig Janeczek > Subject: [PATCH v3 2/8] target/mips: Add all MXU opcodes >=20 > Adds all MXU opcodes to the opcode enum. The MXU opcodes overlap with=20 > existing misc and Loongson 2F copcodes. The enums were updated to=20 > reflect the multiple possible meanings where applicable. >=20 > Signed-off-by: Craig Janeczek It is good that all codes are covered, but this situation with overlap is u= nnatural. Try creating a separate enum for MXU opcodes, and rearranging switch statem= ent, taking into account what instructions set is supported by the CPU in q= uestion.