Re: [PATCH] target/riscv: rvv: Fix missing exit TB flow for ldff_trans

[Richard Henderson <richard.henderson@linaro.org>]

On 6/27/25 06:30, Max Chou wrote:
> According to the V spec, the vector fault-only-first load instructions
> may change the VL CSR.
> So the ldff_trans TCG translation function should generate the
> lookup_and_goto_ptr flow as the vsetvl/vsetvli translation function to
> make sure the vl_eq_vlmax TB flag is correct.
> 
> Signed-off-by: Max Chou <max.chou@sifive.com>
> ---
>   target/riscv/insn_trans/trans_rvv.c.inc | 6 ++++++
>   1 file changed, 6 insertions(+)
> 
> diff --git a/target/riscv/insn_trans/trans_rvv.c.inc b/target/riscv/insn_trans/trans_rvv.c.inc
> index 2b6077ac067..4cd030c7eb3 100644
> --- a/target/riscv/insn_trans/trans_rvv.c.inc
> +++ b/target/riscv/insn_trans/trans_rvv.c.inc
> @@ -1361,6 +1361,12 @@ static bool ldff_trans(uint32_t vd, uint32_t rs1, uint32_t data,
>       fn(dest, mask, base, tcg_env, desc);
>   
>       finalize_rvv_inst(s);
> +
> +    /* vector unit-stride fault-only-first load may modify vl CSR */
> +    gen_update_pc(s, s->cur_insn_len);
> +    lookup_and_goto_ptr(s);
> +    s->base.is_jmp = DISAS_NORETURN;
> +
>       return true;
>   }
>   

Reviewed-by: Richard Henderson <richard.henderson@linaro.org>

r~