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Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.11.0 Subject: Re: [PATCH qemu v4 1/2] target/arm: Handle IC IVAU to improve compatibility with JITs Content-Language: en-US To: ~jhogberg , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org References: <168778890374.24232.3402138851538068785-1@git.sr.ht> From: Richard Henderson In-Reply-To: <168778890374.24232.3402138851538068785-1@git.sr.ht> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::334; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x334.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 6/8/23 19:49, ~jhogberg wrote: > From: John Högberg > > Unlike architectures with precise self-modifying code semantics > (e.g. x86) ARM processors do not maintain coherency for instruction > execution and memory, requiring an instruction synchronization > barrier on every core that will execute the new code, and on many > models also the explicit use of cache management instructions. > > While this is required to make JITs work on actual hardware, QEMU > has gotten away with not handling this since it does not emulate > caches, and unconditionally invalidates code whenever the softmmu > or the user-mode page protection logic detects that code has been > modified. > > Unfortunately the latter does not work in the face of dual-mapped > code (a common W^X workaround), where one page is executable and > the other is writable: user-mode has no way to connect one with the > other as that is only known to the kernel and the emulated > application. > > This commit works around the issue by telling software that > instruction cache invalidation is required by clearing the > CPR_EL0.DIC flag (regardless of whether the emulated processor > needs it), and then invalidating code in IC IVAU instructions. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1034 > > Co-authored-by: Richard Henderson > Signed-off-by: John Högberg > --- > target/arm/cpu.c | 13 +++++++++++++ > target/arm/helper.c | 47 ++++++++++++++++++++++++++++++++++++++++++--- > 2 files changed, 57 insertions(+), 3 deletions(-) > > diff --git a/target/arm/cpu.c b/target/arm/cpu.c > index 4d5bb57f07..b82fb46157 100644 > --- a/target/arm/cpu.c > +++ b/target/arm/cpu.c > @@ -1674,6 +1674,19 @@ static void arm_cpu_realizefn(DeviceState *dev, Error **errp) > return; > } > > + /* > + * User mode relies on IC IVAU instructions to catch modification of > + * dual-mapped code. > + * > + * Clear CTR_EL0.DIC to ensure that software that honors these flags uses > + * IC IVAU even if the emulated processor does not normally require it. > + */ > +#ifdef CONFIG_USER_ONLY > + if (arm_feature(env, ARM_FEATURE_AARCH64)) { > + cpu->ctr = FIELD_DP64(cpu->ctr, CTR_EL0, DIC, 0); > + } > +#endif No need to check for aarch64 -- the bit is present at the same location with the same meaning in the v8 aarch32 view: "CTR". (Prior to v8, this bit was part of the Format field, and had value 0 for v6 and v7, so still no need to check before writing this zero.) Otherwise, Reviewed-by: Richard Henderson r~