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([2806:102e:18:2efc:20f0:1d0e:8e1f:fff0]) by smtp.gmail.com with ESMTPSA id e22-20020a544f16000000b0035aa617156bsm3574705oiy.17.2022.12.12.06.37.56 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 12 Dec 2022 06:37:57 -0800 (PST) Message-ID: Date: Mon, 12 Dec 2022 08:37:54 -0600 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.4.2 Subject: Re: [PATCH-for-8.0 v2 08/11] hw/mips/malta: Use bootloader generator API for nanoMIPS CPUs (3/5) Content-Language: en-US To: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , qemu-devel@nongnu.org Cc: Dragan Mladjenovic , Milica Lazarevic , Jiaxun Yang , Djordje Todorovic , Aurelien Jarno , Bernhard Beschow References: <20221211204533.85359-1-philmd@linaro.org> <20221211204533.85359-9-philmd@linaro.org> From: Richard Henderson In-Reply-To: <20221211204533.85359-9-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::22f; envelope-from=richard.henderson@linaro.org; helo=mail-oi1-x22f.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 12/11/22 14:45, Philippe Mathieu-Daudé wrote: > Part 3/5: Convert PCI0 I/O BAR setup > > Signed-off-by: Philippe Mathieu-Daudé Reviewed-by: Richard Henderson r~ > --- > hw/mips/malta.c | 40 ++++++++-------------------------------- > 1 file changed, 8 insertions(+), 32 deletions(-) > > diff --git a/hw/mips/malta.c b/hw/mips/malta.c > index 3e80a12221..16161b1b03 100644 > --- a/hw/mips/malta.c > +++ b/hw/mips/malta.c > @@ -685,9 +685,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, > > /* > * Load BAR registers as done by YAMON: > - * > - * - set up PCI0 I/O BARs from 0x18000000 to 0x181fffff > - * > */ > stw_p(p++, 0xe040); stw_p(p++, 0x0681); > /* lui t1, %hi(0xb4000000) */ > @@ -707,21 +704,6 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, > > stw_p(p++, 0xe020); stw_p(p++, 0x0801); > /* lui t0, %hi(0xc0000000) */ > - > - /* 0x48 corresponds to GT_PCI0IOLD */ > - stw_p(p++, 0x8422); stw_p(p++, 0x9048); > - /* sw t0, 0x48(t1) */ > - > - stw_p(p++, 0xe020); stw_p(p++, 0x0800); > - /* lui t0, %hi(0x40000000) */ > - > - /* 0x50 corresponds to GT_PCI0IOHD */ > - stw_p(p++, 0x8422); stw_p(p++, 0x9050); > - /* sw t0, 0x50(t1) */ > - > - stw_p(p++, 0xe020); stw_p(p++, 0x0001); > - /* lui t0, %hi(0x80000000) */ > - > #else > #define cpu_to_gt32 cpu_to_be32 > > @@ -738,23 +720,17 @@ static void write_bootloader_nanomips(uint8_t *base, uint64_t run_addr, > > stw_p(p++, 0x0020); stw_p(p++, 0x00c0); > /* addiu[32] t0, $0, 0xc0 */ > - > - /* 0x48 corresponds to GT_PCI0IOLD */ > - stw_p(p++, 0x8422); stw_p(p++, 0x9048); > - /* sw t0, 0x48(t1) */ > - > - stw_p(p++, 0x0020); stw_p(p++, 0x0040); > - /* addiu[32] t0, $0, 0x40 */ > - > - /* 0x50 corresponds to GT_PCI0IOHD */ > - stw_p(p++, 0x8422); stw_p(p++, 0x9050); > - /* sw t0, 0x50(t1) */ > - > - stw_p(p++, 0x0020); stw_p(p++, 0x0080); > - /* addiu[32] t0, $0, 0x80 */ > #endif > v = p; > > + /* setup PCI0 io window to 0x18000000-0x181fffff */ > + bl_gen_write_u32(&v, /* GT_PCI0IOLD */ > + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x48), > + cpu_to_gt32(0x18000000 << 3)); > + bl_gen_write_u32(&v, /* GT_PCI0IOHD */ > + cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x50), > + cpu_to_gt32(0x08000000 << 3)); > + > /* setup PCI0 mem windows */ > bl_gen_write_u32(&v, /* GT_PCI0M0LD */ > cpu_mips_phys_to_kseg1(NULL, 0x1be00000 + 0x58),