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Mon, 19 Aug 2024 22:24:37 -0700 (PDT) Message-ID: Date: Tue, 20 Aug 2024 15:24:27 +1000 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v5 05/15] target/riscv: tracking indirect branches (fcfi) for zicfilp To: Deepak Gupta , qemu-riscv@nongnu.org, qemu-devel@nongnu.org Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com, liwei1518@gmail.com, dbarboza@ventanamicro.com, zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com, andy.chiu@sifive.com, kito.cheng@sifive.com References: <20240820000129.3522346-1-debug@rivosinc.com> <20240820000129.3522346-6-debug@rivosinc.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240820000129.3522346-6-debug@rivosinc.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::529; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x529.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 8/20/24 10:01, Deepak Gupta wrote: > zicfilp protects forward control flow (if enabled) by enforcing all > indirect call and jmp must land on a landing pad instruction `lpad`. If > target of an indirect call or jmp is not `lpad` then cpu/hart must raise > a sw check exception with tval = 2. > > This patch implements the mechanism using TCG. Target architecture branch > instruction must define the end of a TB. Using this property, during > translation of branch instruction, TB flag = FCFI_LP_EXPECTED can be set. > Translation of target TB can check if FCFI_LP_EXPECTED flag is set and a > flag (fcfi_lp_expected) can be set in DisasContext. If `lpad` gets > translated, fcfi_lp_expected flag in DisasContext can be cleared. Else > it'll fault. > > Signed-off-by: Deepak Gupta > Co-developed-by: Jim Shu > Co-developed-by: Andy Chiu > Suggested-by: Richard Henderson > --- > target/riscv/cpu.h | 3 +++ > target/riscv/cpu_bits.h | 3 +++ > target/riscv/cpu_helper.c | 12 ++++++++++++ > target/riscv/translate.c | 21 ++++++++++++++++++++- > 4 files changed, 38 insertions(+), 1 deletion(-) Reviewed-by: Richard Henderson > @@ -1265,11 +1270,25 @@ static void riscv_tr_translate_insn(DisasContextBase *dcbase, CPUState *cpu) > DisasContext *ctx = container_of(dcbase, DisasContext, base); > CPURISCVState *env = cpu_env(cpu); > uint16_t opcode16 = translator_lduw(env, &ctx->base, ctx->base.pc_next); > - > ctx->ol = ctx->xl; > decode_opc(env, ctx, opcode16); > ctx->base.pc_next += ctx->cur_insn_len; Watch the unrelated whitespace changes. r~