Re: [PATCH 04/13] pnv/xive2: Support for "OS LGS Push" TIMA operation

["Cédric Le Goater" <clg@kaod.org>]

On 8/1/24 22:29, Michael Kowal wrote:
> From: Glenn Miles <milesg@linux.vnet.ibm.com>
> 
> Adds support for single byte writes to offset 0x15 of the TIMA address
> space.  This offset holds the Logical Server Group Size (LGS) field.
> The field is used to evenly distribute the interrupt load among the
> members of a group, but is unused in the current implementation so we
> just support the writing of the value for now.
> 
> Signed-off-by: Glenn Miles <milesg@linux.vnet.ibm.com>
> Signed-off-by: Michael Kowal <kowal@linux.ibm.com>


Reviewed-by: Cédric Le Goater <clg@redhat.com>

Thanks,

C.


> ---
>   hw/intc/xive.c | 15 +++++++++++++++
>   1 file changed, 15 insertions(+)
> 
> diff --git a/hw/intc/xive.c b/hw/intc/xive.c
> index 8e62c7e75f..8605dd618f 100644
> --- a/hw/intc/xive.c
> +++ b/hw/intc/xive.c
> @@ -341,6 +341,19 @@ static void xive_tm_set_os_cppr(XivePresenter *xptr, XiveTCTX *tctx,
>       xive_tctx_set_cppr(tctx, TM_QW1_OS, value & 0xff);
>   }
>   
> +static void xive_tctx_set_lgs(XiveTCTX *tctx, uint8_t ring, uint8_t lgs)
> +{
> +    uint8_t *regs = &tctx->regs[ring];
> +
> +    regs[TM_LGS] = lgs;
> +}
> +
> +static void xive_tm_set_os_lgs(XivePresenter *xptr, XiveTCTX *tctx,
> +                          hwaddr offset, uint64_t value, unsigned size)
> +{
> +    xive_tctx_set_lgs(tctx, TM_QW1_OS, value & 0xff);
> +}
> +
>   /*
>    * Adjust the IPB to allow a CPU to process event queues of other
>    * priorities during one physical interrupt cycle.
> @@ -525,6 +538,8 @@ static const XiveTmOp xive2_tm_operations[] = {
>                                                        NULL },
>       { XIVE_TM_HV_PAGE, TM_QW1_OS + TM_WORD2,      4, xive2_tm_push_os_ctx,
>                                                        NULL },
> +    { XIVE_TM_OS_PAGE, TM_QW1_OS + TM_LGS,        1, xive_tm_set_os_lgs,
> +                                                     NULL },
>       { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_CPPR,  1, xive_tm_set_hv_cppr,
>                                                        NULL },
>       { XIVE_TM_HV_PAGE, TM_QW3_HV_PHYS + TM_WORD2, 1, xive_tm_vt_push,