Re: [PATCH 3/5] target/loongarch: Add amcas[_db].{b/h/w/d}

[Richard Henderson <richard.henderson@linaro.org>]

On 10/23/23 08:29, Jiajie Chen wrote:
> +static bool gen_cas(DisasContext *ctx, arg_rrr *a,
> +                    void (*func)(TCGv, TCGv, TCGv, TCGv, TCGArg, MemOp),
> +                    MemOp mop)
> +{
> +    TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
> +    TCGv addr = gpr_src(ctx, a->rj, EXT_NONE);
> +    TCGv val = gpr_src(ctx, a->rk, EXT_NONE);
> +
> +    addr = make_address_i(ctx, addr, 0);
> +
> +    func(dest, addr, dest, val, ctx->mem_idx, mop);

You need

     TCGv old = gpr_src(ctx, a->rd, EXT_NONE);
     func(dest, addr, old, val, ...);

as otherwise rd=0 will abort.

Correct emulation requires that you perform the memory operation, and then discard the 
result.  But you must provide the (initialized) source of zero for that case.

Do any or all of the AM, LL, SC instructions require aligned memory?
I suspect that they do.

I think probably gen_ll, gen_sc, gen_am, and now gen_cas are missing "mop | MO_ALIGN" 
applied to the memory operation(s).


r~