* [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu
@ 2023-08-08 1:54 Jiajie Chen
2023-08-08 1:54 ` [PATCH v4 01/11] target/loongarch: Add macro to check current arch Jiajie Chen
` (10 more replies)
0 siblings, 11 replies; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
This patch series allow qemu-system-loongarch64 to emulate a LoongArch32
machine. A new CPU model is added for loongarch32. Initial GDB support
is added.
At the same time, VA32(32-bit virtual address) support is introduced for
LoongArch64.
LA32 support is tested using a small supervisor program at
https://github.com/jiegec/supervisor-la32. VA32 mode under LA64 is not
tested yet.
Changes since v3:
- Support VA32 mode for LoongArch64
- Check the current arch from CPUCFG.ARCH
- Reject la64-only instructions in la32 mode
Changes since v2:
- Fix typo in previous commit
- Fix VPPN width in TLBEHI/TLBREHI
Changes since v1:
- No longer create a separate qemu-system-loongarch32 executable, but
allow user to run loongarch32 emulation using qemu-system-loongarch64
- Add loongarch32 cpu support for virt machine
Full changes:
Jiajie Chen (11):
target/loongarch: Add macro to check current arch
target/loongarch: Add new object class for loongarch32 cpus
target/loongarch: Add GDB support for loongarch32 mode
target/loongarch: Support LoongArch32 TLB entry
target/loongarch: Support LoongArch32 DMW
target/loongarch: Support LoongArch32 VPPN
target/loongarch: Add LA32 & VA32 to DisasContext
target/loongarch: Reject la64-only instructions in la32 mode
target/loongarch: Truncate high 32 bits of address in VA32 mode
target/loongarch: Sign extend results in VA32 mode
target/loongarch: Add loongarch32 cpu la132
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-base32.xml | 45 ++++++++++
hw/loongarch/virt.c | 5 --
target/loongarch/cpu-csr.h | 22 ++---
target/loongarch/cpu.c | 88 ++++++++++++++++---
target/loongarch/cpu.h | 33 ++++++-
target/loongarch/gdbstub.c | 32 +++++--
target/loongarch/insn_trans/trans_arith.c.inc | 34 +++----
.../loongarch/insn_trans/trans_atomic.c.inc | 77 ++++++++--------
target/loongarch/insn_trans/trans_bit.c.inc | 28 +++---
.../loongarch/insn_trans/trans_branch.c.inc | 9 +-
target/loongarch/insn_trans/trans_extra.c.inc | 16 ++--
.../loongarch/insn_trans/trans_fmemory.c.inc | 8 ++
target/loongarch/insn_trans/trans_fmov.c.inc | 4 +-
target/loongarch/insn_trans/trans_lsx.c.inc | 6 ++
.../loongarch/insn_trans/trans_memory.c.inc | 78 +++++++++-------
target/loongarch/insn_trans/trans_shift.c.inc | 14 +--
target/loongarch/tlb_helper.c | 66 +++++++++++---
target/loongarch/translate.c | 26 ++++++
target/loongarch/translate.h | 12 +++
20 files changed, 430 insertions(+), 175 deletions(-)
create mode 100644 gdb-xml/loongarch-base32.xml
--
2.41.0
^ permalink raw reply [flat|nested] 28+ messages in thread
* [PATCH v4 01/11] target/loongarch: Add macro to check current arch
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 17:01 ` Richard Henderson
2023-08-10 11:06 ` Philippe Mathieu-Daudé
2023-08-08 1:54 ` [PATCH v4 02/11] target/loongarch: Add new object class for loongarch32 cpus Jiajie Chen
` (9 subsequent siblings)
10 siblings, 2 replies; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
Add macro to check if the current cpucfg[1].arch equals to 1(LA32) or
2(LA64).
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu.h | 7 +++++++
1 file changed, 7 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index fa371ca8ba..bf0da8d5b4 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -132,6 +132,13 @@ FIELD(CPUCFG1, HP, 24, 1)
FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
FIELD(CPUCFG1, MSG_INT, 26, 1)
+/* cpucfg[1].arch */
+#define CPUCFG1_ARCH_LA32 1
+#define CPUCFG1_ARCH_LA64 2
+
+#define LOONGARCH_CPUCFG_ARCH(env, mode) \
+ (FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_##mode)
+
/* cpucfg[2] bits */
FIELD(CPUCFG2, FP, 0, 1)
FIELD(CPUCFG2, FP_SP, 1, 1)
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 02/11] target/loongarch: Add new object class for loongarch32 cpus
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
2023-08-08 1:54 ` [PATCH v4 01/11] target/loongarch: Add macro to check current arch Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 18:19 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 03/11] target/loongarch: Add GDB support for loongarch32 mode Jiajie Chen
` (8 subsequent siblings)
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
Add object class for future loongarch32 cpus. It is derived from the
loongarch64 object class.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu.c | 24 ++++++++++++++++++++++++
target/loongarch/cpu.h | 11 +++++++++++
2 files changed, 35 insertions(+)
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index ad93ecac92..3bd293d00a 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -732,6 +732,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
#endif
}
+static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
+{
+}
+
#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
{ \
.parent = TYPE_LOONGARCH_CPU, \
@@ -754,3 +758,23 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
};
DEFINE_TYPES(loongarch_cpu_type_infos)
+
+#define DEFINE_LOONGARCH32_CPU_TYPE(model, initfn) \
+ { \
+ .parent = TYPE_LOONGARCH32_CPU, \
+ .instance_init = initfn, \
+ .name = LOONGARCH_CPU_TYPE_NAME(model), \
+ }
+
+static const TypeInfo loongarch32_cpu_type_infos[] = {
+ {
+ .name = TYPE_LOONGARCH32_CPU,
+ .parent = TYPE_LOONGARCH_CPU,
+ .instance_size = sizeof(LoongArchCPU),
+
+ .abstract = true,
+ .class_size = sizeof(LoongArchCPUClass),
+ .class_init = loongarch32_cpu_class_init,
+ },
+};
+DEFINE_TYPES(loongarch32_cpu_type_infos)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index bf0da8d5b4..396869c3b6 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -404,6 +404,17 @@ struct LoongArchCPUClass {
ResettablePhases parent_phases;
};
+#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
+typedef struct LoongArch32CPUClass LoongArch32CPUClass;
+DECLARE_CLASS_CHECKERS(LoongArch32CPUClass, LOONGARCH32_CPU,
+ TYPE_LOONGARCH32_CPU)
+
+struct LoongArch32CPUClass {
+ /*< private >*/
+ LoongArchCPUClass parent_class;
+ /*< public >*/
+};
+
/*
* LoongArch CPUs has 4 privilege levels.
* 0 for kernel mode, 3 for user mode.
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 03/11] target/loongarch: Add GDB support for loongarch32 mode
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
2023-08-08 1:54 ` [PATCH v4 01/11] target/loongarch: Add macro to check current arch Jiajie Chen
2023-08-08 1:54 ` [PATCH v4 02/11] target/loongarch: Add new object class for loongarch32 cpus Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 18:34 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry Jiajie Chen
` (7 subsequent siblings)
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
GPRs and PC are 32-bit wide in loongarch32 mode.
Signed-off-by: Jiajie Chen <c@jia.je>
---
configs/targets/loongarch64-softmmu.mak | 2 +-
gdb-xml/loongarch-base32.xml | 45 +++++++++++++++++++++++++
target/loongarch/cpu.c | 10 +++++-
target/loongarch/gdbstub.c | 32 ++++++++++++++----
4 files changed, 80 insertions(+), 9 deletions(-)
create mode 100644 gdb-xml/loongarch-base32.xml
diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
index 9abc99056f..f23780fdd8 100644
--- a/configs/targets/loongarch64-softmmu.mak
+++ b/configs/targets/loongarch64-softmmu.mak
@@ -1,5 +1,5 @@
TARGET_ARCH=loongarch64
TARGET_BASE_ARCH=loongarch
TARGET_SUPPORTS_MTTCG=y
-TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
+TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
TARGET_NEED_FDT=y
diff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml
new file mode 100644
index 0000000000..af47bbd3da
--- /dev/null
+++ b/gdb-xml/loongarch-base32.xml
@@ -0,0 +1,45 @@
+<?xml version="1.0"?>
+<!-- Copyright (C) 2022 Free Software Foundation, Inc.
+
+ Copying and distribution of this file, with or without modification,
+ are permitted in any medium without royalty provided the copyright
+ notice and this notice are preserved. -->
+
+<!DOCTYPE feature SYSTEM "gdb-target.dtd">
+<feature name="org.gnu.gdb.loongarch.base">
+ <reg name="r0" bitsize="32" type="uint32" group="general"/>
+ <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
+ <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r4" bitsize="32" type="uint32" group="general"/>
+ <reg name="r5" bitsize="32" type="uint32" group="general"/>
+ <reg name="r6" bitsize="32" type="uint32" group="general"/>
+ <reg name="r7" bitsize="32" type="uint32" group="general"/>
+ <reg name="r8" bitsize="32" type="uint32" group="general"/>
+ <reg name="r9" bitsize="32" type="uint32" group="general"/>
+ <reg name="r10" bitsize="32" type="uint32" group="general"/>
+ <reg name="r11" bitsize="32" type="uint32" group="general"/>
+ <reg name="r12" bitsize="32" type="uint32" group="general"/>
+ <reg name="r13" bitsize="32" type="uint32" group="general"/>
+ <reg name="r14" bitsize="32" type="uint32" group="general"/>
+ <reg name="r15" bitsize="32" type="uint32" group="general"/>
+ <reg name="r16" bitsize="32" type="uint32" group="general"/>
+ <reg name="r17" bitsize="32" type="uint32" group="general"/>
+ <reg name="r18" bitsize="32" type="uint32" group="general"/>
+ <reg name="r19" bitsize="32" type="uint32" group="general"/>
+ <reg name="r20" bitsize="32" type="uint32" group="general"/>
+ <reg name="r21" bitsize="32" type="uint32" group="general"/>
+ <reg name="r22" bitsize="32" type="data_ptr" group="general"/>
+ <reg name="r23" bitsize="32" type="uint32" group="general"/>
+ <reg name="r24" bitsize="32" type="uint32" group="general"/>
+ <reg name="r25" bitsize="32" type="uint32" group="general"/>
+ <reg name="r26" bitsize="32" type="uint32" group="general"/>
+ <reg name="r27" bitsize="32" type="uint32" group="general"/>
+ <reg name="r28" bitsize="32" type="uint32" group="general"/>
+ <reg name="r29" bitsize="32" type="uint32" group="general"/>
+ <reg name="r30" bitsize="32" type="uint32" group="general"/>
+ <reg name="r31" bitsize="32" type="uint32" group="general"/>
+ <reg name="orig_a0" bitsize="32" type="uint32" group="general"/>
+ <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
+ <reg name="badv" bitsize="32" type="code_ptr" group="general"/>
+</feature>
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 3bd293d00a..13d4fccbd3 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -694,7 +694,13 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
static gchar *loongarch_gdb_arch_name(CPUState *cs)
{
- return g_strdup("loongarch64");
+ LoongArchCPU *cpu = LOONGARCH_CPU(cs);
+ CPULoongArchState *env = &cpu->env;
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ return g_strdup("loongarch64");
+ } else {
+ return g_strdup("loongarch32");
+ }
}
static void loongarch_cpu_class_init(ObjectClass *c, void *data)
@@ -734,6 +740,8 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
{
+ CPUClass *cc = CPU_CLASS(c);
+ cc->gdb_core_xml_file = "loongarch-base32.xml";
}
#define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
index 0752fff924..0dfd1c8bb9 100644
--- a/target/loongarch/gdbstub.c
+++ b/target/loongarch/gdbstub.c
@@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
+ uint64_t val;
if (0 <= n && n < 32) {
- return gdb_get_regl(mem_buf, env->gpr[n]);
+ val = env->gpr[n];
} else if (n == 32) {
/* orig_a0 */
- return gdb_get_regl(mem_buf, 0);
+ val = 0;
} else if (n == 33) {
- return gdb_get_regl(mem_buf, env->pc);
+ val = env->pc;
} else if (n == 34) {
- return gdb_get_regl(mem_buf, env->CSR_BADV);
+ val = env->CSR_BADV;
+ }
+
+ if (0 <= n && n <= 34) {
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ return gdb_get_reg64(mem_buf, val);
+ } else {
+ return gdb_get_reg32(mem_buf, val);
+ }
}
return 0;
}
@@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
{
LoongArchCPU *cpu = LOONGARCH_CPU(cs);
CPULoongArchState *env = &cpu->env;
- target_ulong tmp = ldtul_p(mem_buf);
+ target_ulong tmp;
+ int read_length;
int length = 0;
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ tmp = ldq_p(mem_buf);
+ read_length = 8;
+ } else {
+ tmp = ldl_p(mem_buf);
+ read_length = 4;
+ }
+
if (0 <= n && n < 32) {
env->gpr[n] = tmp;
- length = sizeof(target_ulong);
+ length = read_length;
} else if (n == 33) {
env->pc = tmp;
- length = sizeof(target_ulong);
+ length = read_length;
}
return length;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (2 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 03/11] target/loongarch: Add GDB support for loongarch32 mode Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 18:37 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW Jiajie Chen
` (6 subsequent siblings)
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
zero in LoongArch32.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu-csr.h | 9 +++++----
target/loongarch/tlb_helper.c | 17 ++++++++++++-----
2 files changed, 17 insertions(+), 9 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index f8f24032cb..48ed2e0632 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -66,10 +66,11 @@ FIELD(TLBENTRY, D, 1, 1)
FIELD(TLBENTRY, PLV, 2, 2)
FIELD(TLBENTRY, MAT, 4, 2)
FIELD(TLBENTRY, G, 6, 1)
-FIELD(TLBENTRY, PPN, 12, 36)
-FIELD(TLBENTRY, NR, 61, 1)
-FIELD(TLBENTRY, NX, 62, 1)
-FIELD(TLBENTRY, RPLV, 63, 1)
+FIELD(TLBENTRY_32, PPN, 8, 24)
+FIELD(TLBENTRY_64, PPN, 12, 36)
+FIELD(TLBENTRY_64, NR, 61, 1)
+FIELD(TLBENTRY_64, NX, 62, 1)
+FIELD(TLBENTRY_64, RPLV, 63, 1)
#define LOONGARCH_CSR_ASID 0x18 /* Address space identifier */
FIELD(CSR_ASID, ASID, 0, 10)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 6e00190547..f74940ea9f 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -48,10 +48,17 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
tlb_v = FIELD_EX64(tlb_entry, TLBENTRY, V);
tlb_d = FIELD_EX64(tlb_entry, TLBENTRY, D);
tlb_plv = FIELD_EX64(tlb_entry, TLBENTRY, PLV);
- tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY, PPN);
- tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY, NX);
- tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY, NR);
- tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY, RPLV);
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_64, PPN);
+ tlb_nx = FIELD_EX64(tlb_entry, TLBENTRY_64, NX);
+ tlb_nr = FIELD_EX64(tlb_entry, TLBENTRY_64, NR);
+ tlb_rplv = FIELD_EX64(tlb_entry, TLBENTRY_64, RPLV);
+ } else {
+ tlb_ppn = FIELD_EX64(tlb_entry, TLBENTRY_32, PPN);
+ tlb_nx = 0;
+ tlb_nr = 0;
+ tlb_rplv = 0;
+ }
/* Check access rights */
if (!tlb_v) {
@@ -79,7 +86,7 @@ static int loongarch_map_tlb_entry(CPULoongArchState *env, hwaddr *physical,
* tlb_entry contains ppn[47:12] while 16KiB ppn is [47:15]
* need adjust.
*/
- *physical = (tlb_ppn << R_TLBENTRY_PPN_SHIFT) |
+ *physical = (tlb_ppn << R_TLBENTRY_64_PPN_SHIFT) |
(address & MAKE_64BIT_MASK(0, tlb_ps));
*prot = PAGE_READ;
if (tlb_d) {
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (3 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 18:37 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN Jiajie Chen
` (5 subsequent siblings)
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
LA32 uses a different encoding for CSR.DMW and a new direct mapping
mechanism.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu-csr.h | 7 +++----
target/loongarch/tlb_helper.c | 26 +++++++++++++++++++++++---
2 files changed, 26 insertions(+), 7 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index 48ed2e0632..b93f99a9ef 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -188,10 +188,9 @@ FIELD(CSR_DMW, PLV1, 1, 1)
FIELD(CSR_DMW, PLV2, 2, 1)
FIELD(CSR_DMW, PLV3, 3, 1)
FIELD(CSR_DMW, MAT, 4, 2)
-FIELD(CSR_DMW, VSEG, 60, 4)
-
-#define dmw_va2pa(va) \
- (va & MAKE_64BIT_MASK(0, TARGET_VIRT_ADDR_SPACE_BITS))
+FIELD(CSR_DMW_32, PSEG, 25, 3)
+FIELD(CSR_DMW_32, VSEG, 29, 3)
+FIELD(CSR_DMW_64, VSEG, 60, 4)
/* Debug CSRs */
#define LOONGARCH_CSR_DBG 0x500 /* debug config */
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index f74940ea9f..7e26d1c67b 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -173,6 +173,18 @@ static int loongarch_map_address(CPULoongArchState *env, hwaddr *physical,
return TLBRET_NOMATCH;
}
+static hwaddr dmw_va2pa(CPULoongArchState *env, target_ulong va,
+ target_ulong dmw)
+{
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ return va & TARGET_VIRT_MASK;
+ } else {
+ uint32_t pseg = FIELD_EX32(dmw, CSR_DMW_32, PSEG);
+ return (va & MAKE_64BIT_MASK(0, R_CSR_DMW_32_VSEG_SHIFT)) | \
+ (pseg << R_CSR_DMW_32_VSEG_SHIFT);
+ }
+}
+
static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
int *prot, target_ulong address,
MMUAccessType access_type, int mmu_idx)
@@ -192,12 +204,20 @@ static int get_physical_address(CPULoongArchState *env, hwaddr *physical,
}
plv = kernel_mode | (user_mode << R_CSR_DMW_PLV3_SHIFT);
- base_v = address >> R_CSR_DMW_VSEG_SHIFT;
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ base_v = address >> R_CSR_DMW_64_VSEG_SHIFT;
+ } else {
+ base_v = address >> R_CSR_DMW_32_VSEG_SHIFT;
+ }
/* Check direct map window */
for (int i = 0; i < 4; i++) {
- base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW, VSEG);
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_64, VSEG);
+ } else {
+ base_c = FIELD_EX64(env->CSR_DMW[i], CSR_DMW_32, VSEG);
+ }
if ((plv & env->CSR_DMW[i]) && (base_c == base_v)) {
- *physical = dmw_va2pa(address);
+ *physical = dmw_va2pa(env, address, env->CSR_DMW[i]);
*prot = PAGE_READ | PAGE_WRITE | PAGE_EXEC;
return TLBRET_MATCH;
}
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (4 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 18:38 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext Jiajie Chen
` (4 subsequent siblings)
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu-csr.h | 6 ++++--
target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
2 files changed, 22 insertions(+), 7 deletions(-)
diff --git a/target/loongarch/cpu-csr.h b/target/loongarch/cpu-csr.h
index b93f99a9ef..c59d7a9fcb 100644
--- a/target/loongarch/cpu-csr.h
+++ b/target/loongarch/cpu-csr.h
@@ -57,7 +57,8 @@ FIELD(CSR_TLBIDX, PS, 24, 6)
FIELD(CSR_TLBIDX, NE, 31, 1)
#define LOONGARCH_CSR_TLBEHI 0x11 /* TLB EntryHi */
-FIELD(CSR_TLBEHI, VPPN, 13, 35)
+FIELD(CSR_TLBEHI_32, VPPN, 13, 19)
+FIELD(CSR_TLBEHI_64, VPPN, 13, 35)
#define LOONGARCH_CSR_TLBELO0 0x12 /* TLB EntryLo0 */
#define LOONGARCH_CSR_TLBELO1 0x13 /* TLB EntryLo1 */
@@ -164,7 +165,8 @@ FIELD(CSR_TLBRERA, PC, 2, 62)
#define LOONGARCH_CSR_TLBRELO1 0x8d /* TLB refill entrylo1 */
#define LOONGARCH_CSR_TLBREHI 0x8e /* TLB refill entryhi */
FIELD(CSR_TLBREHI, PS, 0, 6)
-FIELD(CSR_TLBREHI, VPPN, 13, 35)
+FIELD(CSR_TLBREHI_32, VPPN, 13, 19)
+FIELD(CSR_TLBREHI_64, VPPN, 13, 35)
#define LOONGARCH_CSR_TLBRPRMD 0x8f /* TLB refill mode info */
FIELD(CSR_TLBRPRMD, PPLV, 0, 2)
FIELD(CSR_TLBRPRMD, PIE, 2, 1)
diff --git a/target/loongarch/tlb_helper.c b/target/loongarch/tlb_helper.c
index 7e26d1c67b..ed4495a301 100644
--- a/target/loongarch/tlb_helper.c
+++ b/target/loongarch/tlb_helper.c
@@ -300,8 +300,13 @@ static void raise_mmu_exception(CPULoongArchState *env, target_ulong address,
if (tlb_error == TLBRET_NOMATCH) {
env->CSR_TLBRBADV = address;
- env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN,
- extract64(address, 13, 35));
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_64,
+ VPPN, extract64(address, 13, 35));
+ } else {
+ env->CSR_TLBREHI = FIELD_DP64(env->CSR_TLBREHI, CSR_TLBREHI_32,
+ VPPN, extract64(address, 13, 19));
+ }
} else {
if (!FIELD_EX64(env->CSR_DBG, CSR_DBG, DST)) {
env->CSR_BADV = address;
@@ -366,12 +371,20 @@ static void fill_tlb_entry(CPULoongArchState *env, int index)
if (FIELD_EX64(env->CSR_TLBRERA, CSR_TLBRERA, ISTLBR)) {
csr_ps = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, PS);
- csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI, VPPN);
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_64, VPPN);
+ } else {
+ csr_vppn = FIELD_EX64(env->CSR_TLBREHI, CSR_TLBREHI_32, VPPN);
+ }
lo0 = env->CSR_TLBRELO0;
lo1 = env->CSR_TLBRELO1;
} else {
csr_ps = FIELD_EX64(env->CSR_TLBIDX, CSR_TLBIDX, PS);
- csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI, VPPN);
+ if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
+ csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_64, VPPN);
+ } else {
+ csr_vppn = FIELD_EX64(env->CSR_TLBEHI, CSR_TLBEHI_32, VPPN);
+ }
lo0 = env->CSR_TLBELO0;
lo1 = env->CSR_TLBELO1;
}
@@ -491,7 +504,7 @@ void helper_tlbfill(CPULoongArchState *env)
if (pagesize == stlb_ps) {
/* Only write into STLB bits [47:13] */
- address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_VPPN_SHIFT);
+ address = entryhi & ~MAKE_64BIT_MASK(0, R_CSR_TLBEHI_64_VPPN_SHIFT);
/* Choose one set ramdomly */
set = get_random_tlb(0, 7);
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (5 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 18:40 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode Jiajie Chen
` (3 subsequent siblings)
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
Add LA32 and VA32(32-bit Virtual Address) to DisasContext to allow the
translator to reject doubleword instructions in LA32 mode for example.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu.h | 9 +++++++++
target/loongarch/translate.c | 3 +++
target/loongarch/translate.h | 2 ++
3 files changed, 14 insertions(+)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 396869c3b6..69589f0aef 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -445,15 +445,24 @@ static inline int cpu_mmu_index(CPULoongArchState *env, bool ifetch)
#define HW_FLAGS_CRMD_PG R_CSR_CRMD_PG_MASK /* 0x10 */
#define HW_FLAGS_EUEN_FPE 0x04
#define HW_FLAGS_EUEN_SXE 0x08
+#define HW_FLAGS_VA32 0x20
static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
uint64_t *cs_base, uint32_t *flags)
{
+ /* VA32 if LA32 or VA32L[1-3] */
+ uint32_t va32 = LOONGARCH_CPUCFG_ARCH(env, LA32);
+ uint64_t plv = FIELD_EX64(env->CSR_CRMD, CSR_CRMD, PLV);
+ if (plv >= 1 && (FIELD_EX64(env->CSR_MISC, CSR_MISC, VA32) & (1 << plv))) {
+ va32 = 1;
+ }
+
*pc = env->pc;
*cs_base = 0;
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, SXE) * HW_FLAGS_EUEN_SXE;
+ *flags |= va32 * HW_FLAGS_VA32;
}
void loongarch_cpu_list(void);
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 3146a2d4ac..f1e5fe4cf8 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -119,6 +119,9 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
ctx->vl = LSX_LEN;
}
+ ctx->la32 = LOONGARCH_CPUCFG_ARCH(env, LA32);
+ ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;
+
ctx->zero = tcg_constant_tl(0);
}
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 7f60090580..828f1185d2 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -33,6 +33,8 @@ typedef struct DisasContext {
uint16_t plv;
int vl; /* Vector length */
TCGv zero;
+ bool la32; /* LoongArch32 mode */
+ bool va32; /* 32-bit virtual address */
} DisasContext;
void generate_exception(DisasContext *ctx, int excp);
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (6 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 18:48 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode Jiajie Chen
` (2 subsequent siblings)
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
LoongArch64-only instructions are marked with regard to the instruction
manual Table 2. LSX instructions are not marked for now for lack of
public manual.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/insn_trans/trans_arith.c.inc | 32 ++++----
.../loongarch/insn_trans/trans_atomic.c.inc | 76 +++++++++----------
target/loongarch/insn_trans/trans_bit.c.inc | 28 +++----
.../loongarch/insn_trans/trans_branch.c.inc | 4 +-
| 16 ++--
target/loongarch/insn_trans/trans_fmov.c.inc | 4 +-
.../loongarch/insn_trans/trans_memory.c.inc | 68 ++++++++---------
target/loongarch/insn_trans/trans_shift.c.inc | 14 ++--
target/loongarch/translate.h | 10 +++
9 files changed, 131 insertions(+), 121 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
index 43d6cf261d..e6d218e84a 100644
--- a/target/loongarch/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
@@ -249,9 +249,9 @@ static bool trans_addu16i_d(DisasContext *ctx, arg_addu16i_d *a)
}
TRANS(add_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_add_tl)
-TRANS(add_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
+TRANS_64(add_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_add_tl)
TRANS(sub_w, gen_rrr, EXT_NONE, EXT_NONE, EXT_SIGN, tcg_gen_sub_tl)
-TRANS(sub_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
+TRANS_64(sub_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_sub_tl)
TRANS(and, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_and_tl)
TRANS(or, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_or_tl)
TRANS(xor, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_xor_tl)
@@ -261,32 +261,32 @@ TRANS(orn, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_orc_tl)
TRANS(slt, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_slt)
TRANS(sltu, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sltu)
TRANS(mul_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, tcg_gen_mul_tl)
-TRANS(mul_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
+TRANS_64(mul_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, tcg_gen_mul_tl)
TRANS(mulh_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, gen_mulh_w)
TRANS(mulh_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, gen_mulh_w)
-TRANS(mulh_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
-TRANS(mulh_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
-TRANS(mulw_d_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
-TRANS(mulw_d_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
+TRANS_64(mulh_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_d)
+TRANS_64(mulh_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_mulh_du)
+TRANS_64(mulw_d_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_NONE, tcg_gen_mul_tl)
+TRANS_64(mulw_d_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_NONE, tcg_gen_mul_tl)
TRANS(div_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_div_w)
TRANS(mod_w, gen_rrr, EXT_SIGN, EXT_SIGN, EXT_SIGN, gen_rem_w)
TRANS(div_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_div_du)
TRANS(mod_wu, gen_rrr, EXT_ZERO, EXT_ZERO, EXT_SIGN, gen_rem_du)
-TRANS(div_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
-TRANS(mod_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
-TRANS(div_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
-TRANS(mod_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
+TRANS_64(div_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_d)
+TRANS_64(mod_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_d)
+TRANS_64(div_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_div_du)
+TRANS_64(mod_du, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rem_du)
TRANS(slti, gen_rri_v, EXT_NONE, EXT_NONE, gen_slt)
TRANS(sltui, gen_rri_v, EXT_NONE, EXT_NONE, gen_sltu)
TRANS(addi_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_addi_tl)
-TRANS(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
-TRANS(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
-TRANS(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
-TRANS(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
+TRANS_64(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
+TRANS_64(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
+TRANS_64(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
+TRANS_64(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
TRANS(pcaddi, gen_pc, gen_pcaddi)
TRANS(pcalau12i, gen_pc, gen_pcalau12i)
TRANS(pcaddu12i, gen_pc, gen_pcaddu12i)
-TRANS(pcaddu18i, gen_pc, gen_pcaddu18i)
+TRANS_64(pcaddu18i, gen_pc, gen_pcaddu18i)
TRANS(andi, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_andi_tl)
TRANS(ori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_ori_tl)
TRANS(xori, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_xori_tl)
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc
index 612709f2a7..c69f31bc78 100644
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
@@ -70,41 +70,41 @@ static bool gen_am(DisasContext *ctx, arg_rrr *a,
TRANS(ll_w, gen_ll, MO_TESL)
TRANS(sc_w, gen_sc, MO_TESL)
-TRANS(ll_d, gen_ll, MO_TEUQ)
-TRANS(sc_d, gen_sc, MO_TEUQ)
-TRANS(amswap_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
-TRANS(amswap_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
-TRANS(amadd_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
-TRANS(amadd_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
-TRANS(amand_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
-TRANS(amand_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
-TRANS(amor_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
-TRANS(amor_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
-TRANS(amxor_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
-TRANS(amxor_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
-TRANS(ammax_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
-TRANS(ammax_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
-TRANS(ammin_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
-TRANS(ammin_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
-TRANS(ammax_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
-TRANS(ammax_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
-TRANS(ammin_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
-TRANS(ammin_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
-TRANS(amswap_db_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
-TRANS(amswap_db_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
-TRANS(amadd_db_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
-TRANS(amadd_db_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
-TRANS(amand_db_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
-TRANS(amand_db_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
-TRANS(amor_db_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
-TRANS(amor_db_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
-TRANS(amxor_db_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
-TRANS(amxor_db_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
-TRANS(ammax_db_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
-TRANS(ammax_db_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
-TRANS(ammin_db_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
-TRANS(ammin_db_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
-TRANS(ammax_db_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
-TRANS(ammax_db_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
-TRANS(ammin_db_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
-TRANS(ammin_db_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
+TRANS_64(ll_d, gen_ll, MO_TEUQ)
+TRANS_64(sc_d, gen_sc, MO_TEUQ)
+TRANS_64(amswap_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
+TRANS_64(amswap_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
+TRANS_64(amadd_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
+TRANS_64(amadd_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
+TRANS_64(amand_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
+TRANS_64(amand_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
+TRANS_64(amor_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
+TRANS_64(amor_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
+TRANS_64(amxor_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
+TRANS_64(amxor_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
+TRANS_64(ammax_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
+TRANS_64(ammax_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
+TRANS_64(ammin_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
+TRANS_64(ammin_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
+TRANS_64(ammax_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
+TRANS_64(ammax_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
+TRANS_64(ammin_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
+TRANS_64(ammin_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
+TRANS_64(amswap_db_w, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL)
+TRANS_64(amswap_db_d, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ)
+TRANS_64(amadd_db_w, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL)
+TRANS_64(amadd_db_d, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ)
+TRANS_64(amand_db_w, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL)
+TRANS_64(amand_db_d, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ)
+TRANS_64(amor_db_w, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL)
+TRANS_64(amor_db_d, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ)
+TRANS_64(amxor_db_w, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL)
+TRANS_64(amxor_db_d, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ)
+TRANS_64(ammax_db_w, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL)
+TRANS_64(ammax_db_d, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ)
+TRANS_64(ammin_db_w, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL)
+TRANS_64(ammin_db_d, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ)
+TRANS_64(ammax_db_wu, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL)
+TRANS_64(ammax_db_du, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ)
+TRANS_64(ammin_db_wu, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL)
+TRANS_64(ammin_db_du, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ)
diff --git a/target/loongarch/insn_trans/trans_bit.c.inc b/target/loongarch/insn_trans/trans_bit.c.inc
index 25b4d7858b..4907b67379 100644
--- a/target/loongarch/insn_trans/trans_bit.c.inc
+++ b/target/loongarch/insn_trans/trans_bit.c.inc
@@ -184,25 +184,25 @@ TRANS(clo_w, gen_rr, EXT_NONE, EXT_NONE, gen_clo_w)
TRANS(clz_w, gen_rr, EXT_ZERO, EXT_NONE, gen_clz_w)
TRANS(cto_w, gen_rr, EXT_NONE, EXT_NONE, gen_cto_w)
TRANS(ctz_w, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_w)
-TRANS(clo_d, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)
-TRANS(clz_d, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)
-TRANS(cto_d, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)
-TRANS(ctz_d, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
+TRANS_64(clo_d, gen_rr, EXT_NONE, EXT_NONE, gen_clo_d)
+TRANS_64(clz_d, gen_rr, EXT_NONE, EXT_NONE, gen_clz_d)
+TRANS_64(cto_d, gen_rr, EXT_NONE, EXT_NONE, gen_cto_d)
+TRANS_64(ctz_d, gen_rr, EXT_NONE, EXT_NONE, gen_ctz_d)
TRANS(revb_2h, gen_rr, EXT_NONE, EXT_SIGN, gen_revb_2h)
-TRANS(revb_4h, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
-TRANS(revb_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
-TRANS(revb_d, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
-TRANS(revh_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
-TRANS(revh_d, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
+TRANS_64(revb_4h, gen_rr, EXT_NONE, EXT_NONE, gen_revb_4h)
+TRANS_64(revb_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revb_2w)
+TRANS_64(revb_d, gen_rr, EXT_NONE, EXT_NONE, tcg_gen_bswap64_i64)
+TRANS_64(revh_2w, gen_rr, EXT_NONE, EXT_NONE, gen_revh_2w)
+TRANS_64(revh_d, gen_rr, EXT_NONE, EXT_NONE, gen_revh_d)
TRANS(bitrev_4b, gen_rr, EXT_ZERO, EXT_SIGN, gen_helper_bitswap)
-TRANS(bitrev_8b, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
+TRANS_64(bitrev_8b, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitswap)
TRANS(bitrev_w, gen_rr, EXT_NONE, EXT_SIGN, gen_helper_bitrev_w)
-TRANS(bitrev_d, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
+TRANS_64(bitrev_d, gen_rr, EXT_NONE, EXT_NONE, gen_helper_bitrev_d)
TRANS(maskeqz, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_maskeqz)
TRANS(masknez, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_masknez)
TRANS(bytepick_w, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_w)
-TRANS(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
+TRANS_64(bytepick_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_bytepick_d)
TRANS(bstrins_w, gen_bstrins, EXT_SIGN)
-TRANS(bstrins_d, gen_bstrins, EXT_NONE)
+TRANS_64(bstrins_d, gen_bstrins, EXT_NONE)
TRANS(bstrpick_w, gen_bstrpick, EXT_SIGN)
-TRANS(bstrpick_d, gen_bstrpick, EXT_NONE)
+TRANS_64(bstrpick_d, gen_bstrpick, EXT_NONE)
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
index a860f7e733..29b81a9843 100644
--- a/target/loongarch/insn_trans/trans_branch.c.inc
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -79,5 +79,5 @@ TRANS(bltu, gen_rr_bc, TCG_COND_LTU)
TRANS(bgeu, gen_rr_bc, TCG_COND_GEU)
TRANS(beqz, gen_rz_bc, TCG_COND_EQ)
TRANS(bnez, gen_rz_bc, TCG_COND_NE)
-TRANS(bceqz, gen_cz_bc, TCG_COND_EQ)
-TRANS(bcnez, gen_cz_bc, TCG_COND_NE)
+TRANS_64(bceqz, gen_cz_bc, TCG_COND_EQ)
+TRANS_64(bcnez, gen_cz_bc, TCG_COND_NE)
--git a/target/loongarch/insn_trans/trans_extra.c.inc b/target/loongarch/insn_trans/trans_extra.c.inc
index 06f4de4515..596f707c45 100644
--- a/target/loongarch/insn_trans/trans_extra.c.inc
+++ b/target/loongarch/insn_trans/trans_extra.c.inc
@@ -89,11 +89,11 @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a,
return true;
}
-TRANS(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
-TRANS(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
-TRANS(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
-TRANS(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
-TRANS(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
-TRANS(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
-TRANS(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
-TRANS(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
+TRANS_64(crc_w_b_w, gen_crc, gen_helper_crc32, tcg_constant_tl(1))
+TRANS_64(crc_w_h_w, gen_crc, gen_helper_crc32, tcg_constant_tl(2))
+TRANS_64(crc_w_w_w, gen_crc, gen_helper_crc32, tcg_constant_tl(4))
+TRANS_64(crc_w_d_w, gen_crc, gen_helper_crc32, tcg_constant_tl(8))
+TRANS_64(crcc_w_b_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(1))
+TRANS_64(crcc_w_h_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(2))
+TRANS_64(crcc_w_w_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(4))
+TRANS_64(crcc_w_d_w, gen_crc, gen_helper_crc32c, tcg_constant_tl(8))
diff --git a/target/loongarch/insn_trans/trans_fmov.c.inc b/target/loongarch/insn_trans/trans_fmov.c.inc
index 5af0dd1b66..c58c5c6534 100644
--- a/target/loongarch/insn_trans/trans_fmov.c.inc
+++ b/target/loongarch/insn_trans/trans_fmov.c.inc
@@ -181,8 +181,8 @@ static bool trans_movcf2gr(DisasContext *ctx, arg_movcf2gr *a)
TRANS(fmov_s, gen_f2f, tcg_gen_mov_tl, true)
TRANS(fmov_d, gen_f2f, tcg_gen_mov_tl, false)
TRANS(movgr2fr_w, gen_r2f, gen_movgr2fr_w)
-TRANS(movgr2fr_d, gen_r2f, tcg_gen_mov_tl)
+TRANS_64(movgr2fr_d, gen_r2f, tcg_gen_mov_tl)
TRANS(movgr2frh_w, gen_r2f, gen_movgr2frh_w)
TRANS(movfr2gr_s, gen_f2r, tcg_gen_ext32s_tl)
-TRANS(movfr2gr_d, gen_f2r, tcg_gen_mov_tl)
+TRANS_64(movfr2gr_d, gen_f2r, tcg_gen_mov_tl)
TRANS(movfrh2gr_s, gen_f2r, gen_movfrh2gr_s)
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
index 75cfdf59ad..858c97951b 100644
--- a/target/loongarch/insn_trans/trans_memory.c.inc
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
@@ -162,42 +162,42 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
TRANS(ld_b, gen_load, MO_SB)
TRANS(ld_h, gen_load, MO_TESW)
TRANS(ld_w, gen_load, MO_TESL)
-TRANS(ld_d, gen_load, MO_TEUQ)
+TRANS_64(ld_d, gen_load, MO_TEUQ)
TRANS(st_b, gen_store, MO_UB)
TRANS(st_h, gen_store, MO_TEUW)
TRANS(st_w, gen_store, MO_TEUL)
-TRANS(st_d, gen_store, MO_TEUQ)
+TRANS_64(st_d, gen_store, MO_TEUQ)
TRANS(ld_bu, gen_load, MO_UB)
TRANS(ld_hu, gen_load, MO_TEUW)
-TRANS(ld_wu, gen_load, MO_TEUL)
-TRANS(ldx_b, gen_loadx, MO_SB)
-TRANS(ldx_h, gen_loadx, MO_TESW)
-TRANS(ldx_w, gen_loadx, MO_TESL)
-TRANS(ldx_d, gen_loadx, MO_TEUQ)
-TRANS(stx_b, gen_storex, MO_UB)
-TRANS(stx_h, gen_storex, MO_TEUW)
-TRANS(stx_w, gen_storex, MO_TEUL)
-TRANS(stx_d, gen_storex, MO_TEUQ)
-TRANS(ldx_bu, gen_loadx, MO_UB)
-TRANS(ldx_hu, gen_loadx, MO_TEUW)
-TRANS(ldx_wu, gen_loadx, MO_TEUL)
-TRANS(ldptr_w, gen_ldptr, MO_TESL)
-TRANS(stptr_w, gen_stptr, MO_TEUL)
-TRANS(ldptr_d, gen_ldptr, MO_TEUQ)
-TRANS(stptr_d, gen_stptr, MO_TEUQ)
-TRANS(ldgt_b, gen_load_gt, MO_SB)
-TRANS(ldgt_h, gen_load_gt, MO_TESW)
-TRANS(ldgt_w, gen_load_gt, MO_TESL)
-TRANS(ldgt_d, gen_load_gt, MO_TEUQ)
-TRANS(ldle_b, gen_load_le, MO_SB)
-TRANS(ldle_h, gen_load_le, MO_TESW)
-TRANS(ldle_w, gen_load_le, MO_TESL)
-TRANS(ldle_d, gen_load_le, MO_TEUQ)
-TRANS(stgt_b, gen_store_gt, MO_UB)
-TRANS(stgt_h, gen_store_gt, MO_TEUW)
-TRANS(stgt_w, gen_store_gt, MO_TEUL)
-TRANS(stgt_d, gen_store_gt, MO_TEUQ)
-TRANS(stle_b, gen_store_le, MO_UB)
-TRANS(stle_h, gen_store_le, MO_TEUW)
-TRANS(stle_w, gen_store_le, MO_TEUL)
-TRANS(stle_d, gen_store_le, MO_TEUQ)
+TRANS_64(ld_wu, gen_load, MO_TEUL)
+TRANS_64(ldx_b, gen_loadx, MO_SB)
+TRANS_64(ldx_h, gen_loadx, MO_TESW)
+TRANS_64(ldx_w, gen_loadx, MO_TESL)
+TRANS_64(ldx_d, gen_loadx, MO_TEUQ)
+TRANS_64(stx_b, gen_storex, MO_UB)
+TRANS_64(stx_h, gen_storex, MO_TEUW)
+TRANS_64(stx_w, gen_storex, MO_TEUL)
+TRANS_64(stx_d, gen_storex, MO_TEUQ)
+TRANS_64(ldx_bu, gen_loadx, MO_UB)
+TRANS_64(ldx_hu, gen_loadx, MO_TEUW)
+TRANS_64(ldx_wu, gen_loadx, MO_TEUL)
+TRANS_64(ldptr_w, gen_ldptr, MO_TESL)
+TRANS_64(stptr_w, gen_stptr, MO_TEUL)
+TRANS_64(ldptr_d, gen_ldptr, MO_TEUQ)
+TRANS_64(stptr_d, gen_stptr, MO_TEUQ)
+TRANS_64(ldgt_b, gen_load_gt, MO_SB)
+TRANS_64(ldgt_h, gen_load_gt, MO_TESW)
+TRANS_64(ldgt_w, gen_load_gt, MO_TESL)
+TRANS_64(ldgt_d, gen_load_gt, MO_TEUQ)
+TRANS_64(ldle_b, gen_load_le, MO_SB)
+TRANS_64(ldle_h, gen_load_le, MO_TESW)
+TRANS_64(ldle_w, gen_load_le, MO_TESL)
+TRANS_64(ldle_d, gen_load_le, MO_TEUQ)
+TRANS_64(stgt_b, gen_store_gt, MO_UB)
+TRANS_64(stgt_h, gen_store_gt, MO_TEUW)
+TRANS_64(stgt_w, gen_store_gt, MO_TEUL)
+TRANS_64(stgt_d, gen_store_gt, MO_TEUQ)
+TRANS_64(stle_b, gen_store_le, MO_UB)
+TRANS_64(stle_h, gen_store_le, MO_TEUW)
+TRANS_64(stle_w, gen_store_le, MO_TEUL)
+TRANS_64(stle_d, gen_store_le, MO_TEUQ)
diff --git a/target/loongarch/insn_trans/trans_shift.c.inc b/target/loongarch/insn_trans/trans_shift.c.inc
index bf5428a2ba..7bbbfe6c8c 100644
--- a/target/loongarch/insn_trans/trans_shift.c.inc
+++ b/target/loongarch/insn_trans/trans_shift.c.inc
@@ -81,15 +81,15 @@ static bool trans_srai_w(DisasContext *ctx, arg_srai_w *a)
TRANS(sll_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_sll_w)
TRANS(srl_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_srl_w)
TRANS(sra_w, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w)
-TRANS(sll_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
-TRANS(srl_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
-TRANS(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
+TRANS_64(sll_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d)
+TRANS_64(srl_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d)
+TRANS_64(sra_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d)
TRANS(rotr_w, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w)
-TRANS(rotr_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
+TRANS_64(rotr_d, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d)
TRANS(slli_w, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl)
-TRANS(slli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
+TRANS_64(slli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl)
TRANS(srli_w, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl)
TRANS(srli_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl)
-TRANS(srai_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
+TRANS_64(srai_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl)
TRANS(rotri_w, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w)
-TRANS(rotri_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
+TRANS_64(rotri_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl)
diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
index 828f1185d2..049b8f4570 100644
--- a/target/loongarch/translate.h
+++ b/target/loongarch/translate.h
@@ -14,6 +14,16 @@
static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
{ return FUNC(ctx, a, __VA_ARGS__); }
+/* for LoongArch64-only instructions */
+#define TRANS_64(NAME, FUNC, ...) \
+ static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
+ { \
+ if (ctx->la32) { \
+ return false; \
+ } \
+ return FUNC(ctx, a, __VA_ARGS__); \
+ }
+
/*
* If an operation is being performed on less than TARGET_LONG_BITS,
* it may require the inputs to be sign- or zero-extended; which will
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (7 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 19:08 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 10/11] target/loongarch: Sign extend results " Jiajie Chen
2023-08-08 1:54 ` [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132 Jiajie Chen
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
When running in VA32 mode(LA32 or VA32L[1-3] matching PLV), virtual
address is truncated to 32 bits before address mapping.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/cpu.h | 6 +++++-
target/loongarch/insn_trans/trans_atomic.c.inc | 1 +
target/loongarch/insn_trans/trans_fmemory.c.inc | 8 ++++++++
target/loongarch/insn_trans/trans_lsx.c.inc | 6 ++++++
target/loongarch/insn_trans/trans_memory.c.inc | 10 ++++++++++
target/loongarch/translate.c | 10 ++++++++++
6 files changed, 40 insertions(+), 1 deletion(-)
diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
index 69589f0aef..9ad5fcc494 100644
--- a/target/loongarch/cpu.h
+++ b/target/loongarch/cpu.h
@@ -457,7 +457,11 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
va32 = 1;
}
- *pc = env->pc;
+ if (va32) {
+ *pc = (uint32_t)env->pc;
+ } else {
+ *pc = env->pc;
+ }
*cs_base = 0;
*flags = env->CSR_CRMD & (R_CSR_CRMD_PLV_MASK | R_CSR_CRMD_PG_MASK);
*flags |= FIELD_EX64(env->CSR_EUEN, CSR_EUEN, FPE) * HW_FLAGS_EUEN_FPE;
diff --git a/target/loongarch/insn_trans/trans_atomic.c.inc b/target/loongarch/insn_trans/trans_atomic.c.inc
index c69f31bc78..d9d950d642 100644
--- a/target/loongarch/insn_trans/trans_atomic.c.inc
+++ b/target/loongarch/insn_trans/trans_atomic.c.inc
@@ -10,6 +10,7 @@ static bool gen_ll(DisasContext *ctx, arg_rr_i *a, MemOp mop)
TCGv t0 = tcg_temp_new();
tcg_gen_addi_tl(t0, src1, a->imm);
+ t0 = va32_address(ctx, t0);
tcg_gen_qemu_ld_i64(dest, t0, ctx->mem_idx, mop);
tcg_gen_st_tl(t0, cpu_env, offsetof(CPULoongArchState, lladdr));
tcg_gen_st_tl(dest, cpu_env, offsetof(CPULoongArchState, llval));
diff --git a/target/loongarch/insn_trans/trans_fmemory.c.inc b/target/loongarch/insn_trans/trans_fmemory.c.inc
index 91c09fb6d9..391af356d0 100644
--- a/target/loongarch/insn_trans/trans_fmemory.c.inc
+++ b/target/loongarch/insn_trans/trans_fmemory.c.inc
@@ -22,6 +22,7 @@ static bool gen_fload_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
@@ -42,6 +43,7 @@ static bool gen_fstore_i(DisasContext *ctx, arg_fr_i *a, MemOp mop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_st_tl(src, addr, ctx->mem_idx, mop);
@@ -59,6 +61,7 @@ static bool gen_floadx(DisasContext *ctx, arg_frr *a, MemOp mop)
addr = tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);
@@ -77,6 +80,7 @@ static bool gen_fstorex(DisasContext *ctx, arg_frr *a, MemOp mop)
addr = tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
return true;
@@ -94,6 +98,7 @@ static bool gen_fload_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
addr = tcg_temp_new();
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);
@@ -113,6 +118,7 @@ static bool gen_fstore_gt(DisasContext *ctx, arg_frr *a, MemOp mop)
addr = tcg_temp_new();
gen_helper_asrtgt_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
return true;
@@ -130,6 +136,7 @@ static bool gen_fload_le(DisasContext *ctx, arg_frr *a, MemOp mop)
addr = tcg_temp_new();
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
maybe_nanbox_load(dest, mop);
set_fpr(a->fd, dest);
@@ -149,6 +156,7 @@ static bool gen_fstore_le(DisasContext *ctx, arg_frr *a, MemOp mop)
addr = tcg_temp_new();
gen_helper_asrtle_d(cpu_env, src1, src2);
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_st_tl(src3, addr, ctx->mem_idx, mop);
return true;
diff --git a/target/loongarch/insn_trans/trans_lsx.c.inc b/target/loongarch/insn_trans/trans_lsx.c.inc
index 68779daff6..b7325cfd8a 100644
--- a/target/loongarch/insn_trans/trans_lsx.c.inc
+++ b/target/loongarch/insn_trans/trans_lsx.c.inc
@@ -4271,6 +4271,7 @@ static bool trans_vld(DisasContext *ctx, arg_vr_i *a)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE);
tcg_gen_extr_i128_i64(rl, rh, val);
@@ -4298,6 +4299,7 @@ static bool trans_vst(DisasContext *ctx, arg_vr_i *a)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
get_vreg64(ah, a->vd, 1);
get_vreg64(al, a->vd, 0);
@@ -4323,6 +4325,7 @@ static bool trans_vldx(DisasContext *ctx, arg_vrr *a)
rh = tcg_temp_new_i64();
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_i128(val, addr, ctx->mem_idx, MO_128 | MO_TE);
tcg_gen_extr_i128_i64(rl, rh, val);
set_vreg64(rh, a->vd, 1);
@@ -4347,6 +4350,7 @@ static bool trans_vstx(DisasContext *ctx, arg_vrr *a)
al = tcg_temp_new_i64();
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
get_vreg64(ah, a->vd, 1);
get_vreg64(al, a->vd, 0);
tcg_gen_concat_i64_i128(val, al, ah);
@@ -4371,6 +4375,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_i *a) \
tcg_gen_addi_tl(temp, addr, a->imm); \
addr = temp; \
} \
+ addr = va32_address(ctx, addr); \
\
tcg_gen_qemu_ld_i64(val, addr, ctx->mem_idx, MO); \
tcg_gen_gvec_dup_i64(MO, vec_full_offset(a->vd), 16, ctx->vl/8, val); \
@@ -4399,6 +4404,7 @@ static bool trans_## NAME (DisasContext *ctx, arg_vr_ii *a) \
tcg_gen_addi_tl(temp, addr, a->imm); \
addr = temp; \
} \
+ addr = va32_address(ctx, addr); \
\
tcg_gen_ld_i64(val, cpu_env, \
offsetof(CPULoongArchState, fpr[a->vd].vreg.E(a->imm2))); \
diff --git a/target/loongarch/insn_trans/trans_memory.c.inc b/target/loongarch/insn_trans/trans_memory.c.inc
index 858c97951b..5b45444be4 100644
--- a/target/loongarch/insn_trans/trans_memory.c.inc
+++ b/target/loongarch/insn_trans/trans_memory.c.inc
@@ -13,6 +13,7 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -29,6 +30,7 @@ static bool gen_store(DisasContext *ctx, arg_rr_i *a, MemOp mop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
return true;
@@ -42,6 +44,7 @@ static bool gen_loadx(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv addr = tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -56,6 +59,7 @@ static bool gen_storex(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv addr = tcg_temp_new();
tcg_gen_add_tl(addr, src1, src2);
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
return true;
@@ -68,6 +72,7 @@ static bool gen_load_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtgt_d(cpu_env, src1, src2);
+ src1 = va32_address(ctx, src1);
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -81,6 +86,7 @@ static bool gen_load_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtle_d(cpu_env, src1, src2);
+ src1 = va32_address(ctx, src1);
tcg_gen_qemu_ld_tl(dest, src1, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -94,6 +100,7 @@ static bool gen_store_gt(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtgt_d(cpu_env, src1, src2);
+ src1 = va32_address(ctx, src1);
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
return true;
@@ -106,6 +113,7 @@ static bool gen_store_le(DisasContext *ctx, arg_rrr *a, MemOp mop)
TCGv src2 = gpr_src(ctx, a->rk, EXT_NONE);
gen_helper_asrtle_d(cpu_env, src1, src2);
+ src1 = va32_address(ctx, src1);
tcg_gen_qemu_st_tl(data, src1, ctx->mem_idx, mop);
return true;
@@ -138,6 +146,7 @@ static bool gen_ldptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_ld_tl(dest, addr, ctx->mem_idx, mop);
gen_set_gpr(a->rd, dest, EXT_NONE);
@@ -154,6 +163,7 @@ static bool gen_stptr(DisasContext *ctx, arg_rr_i *a, MemOp mop)
tcg_gen_addi_tl(temp, addr, a->imm);
addr = temp;
}
+ addr = va32_address(ctx, addr);
tcg_gen_qemu_st_tl(data, addr, ctx->mem_idx, mop);
return true;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index f1e5fe4cf8..9cd2f13778 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -208,6 +208,16 @@ static void set_fpr(int reg_num, TCGv val)
offsetof(CPULoongArchState, fpr[reg_num].vreg.D(0)));
}
+static TCGv va32_address(DisasContext *ctx, TCGv addr)
+{
+ if (ctx->va32) {
+ TCGv temp = tcg_temp_new();
+ tcg_gen_ext32u_tl(temp, addr);
+ addr = temp;
+ }
+ return addr;
+}
+
#include "decode-insns.c.inc"
#include "insn_trans/trans_arith.c.inc"
#include "insn_trans/trans_shift.c.inc"
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 10/11] target/loongarch: Sign extend results in VA32 mode
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (8 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 19:12 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132 Jiajie Chen
10 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
In VA32 mode, BL, JIRL and PC* instructions should sign-extend the low
32 bit result to 64 bits.
Signed-off-by: Jiajie Chen <c@jia.je>
---
target/loongarch/insn_trans/trans_arith.c.inc | 2 +-
target/loongarch/insn_trans/trans_branch.c.inc | 5 +++--
target/loongarch/translate.c | 13 +++++++++++++
3 files changed, 17 insertions(+), 3 deletions(-)
diff --git a/target/loongarch/insn_trans/trans_arith.c.inc b/target/loongarch/insn_trans/trans_arith.c.inc
index e6d218e84a..39915f228d 100644
--- a/target/loongarch/insn_trans/trans_arith.c.inc
+++ b/target/loongarch/insn_trans/trans_arith.c.inc
@@ -72,7 +72,7 @@ static bool gen_pc(DisasContext *ctx, arg_r_i *a,
target_ulong (*func)(target_ulong, int))
{
TCGv dest = gpr_dst(ctx, a->rd, EXT_NONE);
- target_ulong addr = func(ctx->base.pc_next, a->imm);
+ target_ulong addr = va32_result(ctx, func(ctx->base.pc_next, a->imm));
tcg_gen_movi_tl(dest, addr);
gen_set_gpr(a->rd, dest, EXT_NONE);
diff --git a/target/loongarch/insn_trans/trans_branch.c.inc b/target/loongarch/insn_trans/trans_branch.c.inc
index 29b81a9843..41f0bfd489 100644
--- a/target/loongarch/insn_trans/trans_branch.c.inc
+++ b/target/loongarch/insn_trans/trans_branch.c.inc
@@ -12,7 +12,7 @@ static bool trans_b(DisasContext *ctx, arg_b *a)
static bool trans_bl(DisasContext *ctx, arg_bl *a)
{
- tcg_gen_movi_tl(cpu_gpr[1], ctx->base.pc_next + 4);
+ tcg_gen_movi_tl(cpu_gpr[1], va32_result(ctx, ctx->base.pc_next + 4));
gen_goto_tb(ctx, 0, ctx->base.pc_next + a->offs);
ctx->base.is_jmp = DISAS_NORETURN;
return true;
@@ -24,7 +24,8 @@ static bool trans_jirl(DisasContext *ctx, arg_jirl *a)
TCGv src1 = gpr_src(ctx, a->rj, EXT_NONE);
tcg_gen_addi_tl(cpu_pc, src1, a->imm);
- tcg_gen_movi_tl(dest, ctx->base.pc_next + 4);
+ tcg_gen_movi_tl(dest, va32_result(ctx, ctx->base.pc_next + 4));
+
gen_set_gpr(a->rd, dest, EXT_NONE);
tcg_gen_lookup_and_goto_ptr();
ctx->base.is_jmp = DISAS_NORETURN;
diff --git a/target/loongarch/translate.c b/target/loongarch/translate.c
index 9cd2f13778..9703fc46a6 100644
--- a/target/loongarch/translate.c
+++ b/target/loongarch/translate.c
@@ -218,6 +218,19 @@ static TCGv va32_address(DisasContext *ctx, TCGv addr)
return addr;
}
+static uint64_t sign_extend32(uint64_t data)
+{
+ return (data & 0x7FFFFFFF) - (data & 0x80000000);
+}
+
+static uint64_t va32_result(DisasContext *ctx, uint64_t addr)
+{
+ if (ctx->va32) {
+ addr = sign_extend32(addr);
+ }
+ return addr;
+}
+
#include "decode-insns.c.inc"
#include "insn_trans/trans_arith.c.inc"
#include "insn_trans/trans_shift.c.inc"
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
` (9 preceding siblings ...)
2023-08-08 1:54 ` [PATCH v4 10/11] target/loongarch: Sign extend results " Jiajie Chen
@ 2023-08-08 1:54 ` Jiajie Chen
2023-08-08 1:59 ` Jiajie Chen
2023-08-08 19:26 ` Richard Henderson
10 siblings, 2 replies; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:54 UTC (permalink / raw)
To: qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu,
Jiajie Chen
Add la132 as a loongarch32 cpu type and allow virt machine to be used
with la132 instead of la464.
Refactor common init logic out as loongarch_cpu_initfn_common.
Signed-off-by: Jiajie Chen <c@jia.je>
---
hw/loongarch/virt.c | 5 ----
target/loongarch/cpu.c | 54 ++++++++++++++++++++++++++++++++----------
2 files changed, 41 insertions(+), 18 deletions(-)
diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
index e19b042ce8..af15bf5aaa 100644
--- a/hw/loongarch/virt.c
+++ b/hw/loongarch/virt.c
@@ -798,11 +798,6 @@ static void loongarch_init(MachineState *machine)
cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
}
- if (!strstr(cpu_model, "la464")) {
- error_report("LoongArch/TCG needs cpu type la464");
- exit(1);
- }
-
if (ram_size < 1 * GiB) {
error_report("ram_size must be greater than 1G.");
exit(1);
diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
index 13d4fccbd3..341176817e 100644
--- a/target/loongarch/cpu.c
+++ b/target/loongarch/cpu.c
@@ -356,30 +356,18 @@ static bool loongarch_cpu_has_work(CPUState *cs)
#endif
}
-static void loongarch_la464_initfn(Object *obj)
+static void loongarch_cpu_initfn_common(CPULoongArchState *env)
{
- LoongArchCPU *cpu = LOONGARCH_CPU(obj);
- CPULoongArchState *env = &cpu->env;
int i;
for (i = 0; i < 21; i++) {
env->cpucfg[i] = 0x0;
}
- cpu->dtb_compatible = "loongarch,Loongson-3A5000";
- env->cpucfg[0] = 0x14c010; /* PRID */
-
uint32_t data = 0;
- data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
- data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f);
- data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f);
data = FIELD_DP32(data, CPUCFG1, UAL, 1);
- data = FIELD_DP32(data, CPUCFG1, RI, 1);
- data = FIELD_DP32(data, CPUCFG1, EP, 1);
- data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
- data = FIELD_DP32(data, CPUCFG1, HP, 1);
data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
env->cpucfg[1] = data;
@@ -439,6 +427,45 @@ static void loongarch_la464_initfn(Object *obj)
env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
}
+static void loongarch_la464_initfn(Object *obj)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+ CPULoongArchState *env = &cpu->env;
+
+ loongarch_cpu_initfn_common(env);
+
+ cpu->dtb_compatible = "loongarch,Loongson-3A5000";
+ env->cpucfg[0] = 0x14c010; /* PRID */
+
+ uint32_t data = env->cpucfg[1];
+ data = FIELD_DP32(data, CPUCFG1, ARCH, 2); /* LA64 */
+ data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); /* 48 bits */
+ data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); /* 48 bits */
+ data = FIELD_DP32(data, CPUCFG1, RI, 1);
+ data = FIELD_DP32(data, CPUCFG1, EP, 1);
+ data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
+ env->cpucfg[1] = data;
+}
+
+static void loongarch_la132_initfn(Object *obj)
+{
+ LoongArchCPU *cpu = LOONGARCH_CPU(obj);
+ CPULoongArchState *env = &cpu->env;
+
+ loongarch_cpu_initfn_common(env);
+
+ cpu->dtb_compatible = "loongarch,Loongson-1C103";
+
+ uint32_t data = env->cpucfg[1];
+ data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
+ data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
+ data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
+ data = FIELD_DP32(data, CPUCFG1, RI, 0);
+ data = FIELD_DP32(data, CPUCFG1, EP, 0);
+ data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
+ env->cpucfg[1] = data;
+}
+
static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
{
const char *typename = object_class_get_name(OBJECT_CLASS(data));
@@ -784,5 +811,6 @@ static const TypeInfo loongarch32_cpu_type_infos[] = {
.class_size = sizeof(LoongArchCPUClass),
.class_init = loongarch32_cpu_class_init,
},
+ DEFINE_LOONGARCH32_CPU_TYPE("la132", loongarch_la132_initfn),
};
DEFINE_TYPES(loongarch32_cpu_type_infos)
--
2.41.0
^ permalink raw reply related [flat|nested] 28+ messages in thread
* Re: [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132
2023-08-08 1:54 ` [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132 Jiajie Chen
@ 2023-08-08 1:59 ` Jiajie Chen
2023-08-08 19:26 ` Richard Henderson
1 sibling, 0 replies; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 1:59 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu
On 2023/8/8 09:54, Jiajie Chen wrote:
> Add la132 as a loongarch32 cpu type and allow virt machine to be used
> with la132 instead of la464.
>
> Refactor common init logic out as loongarch_cpu_initfn_common.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> hw/loongarch/virt.c | 5 ----
> target/loongarch/cpu.c | 54 ++++++++++++++++++++++++++++++++----------
> 2 files changed, 41 insertions(+), 18 deletions(-)
>
> diff --git a/hw/loongarch/virt.c b/hw/loongarch/virt.c
> index e19b042ce8..af15bf5aaa 100644
> --- a/hw/loongarch/virt.c
> +++ b/hw/loongarch/virt.c
> @@ -798,11 +798,6 @@ static void loongarch_init(MachineState *machine)
> cpu_model = LOONGARCH_CPU_TYPE_NAME("la464");
> }
>
> - if (!strstr(cpu_model, "la464")) {
> - error_report("LoongArch/TCG needs cpu type la464");
> - exit(1);
> - }
> -
> if (ram_size < 1 * GiB) {
> error_report("ram_size must be greater than 1G.");
> exit(1);
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 13d4fccbd3..341176817e 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -356,30 +356,18 @@ static bool loongarch_cpu_has_work(CPUState *cs)
> #endif
> }
>
> -static void loongarch_la464_initfn(Object *obj)
> +static void loongarch_cpu_initfn_common(CPULoongArchState *env)
> {
> - LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> - CPULoongArchState *env = &cpu->env;
> int i;
>
> for (i = 0; i < 21; i++) {
> env->cpucfg[i] = 0x0;
> }
>
> - cpu->dtb_compatible = "loongarch,Loongson-3A5000";
> - env->cpucfg[0] = 0x14c010; /* PRID */
> -
> uint32_t data = 0;
> - data = FIELD_DP32(data, CPUCFG1, ARCH, 2);
> data = FIELD_DP32(data, CPUCFG1, PGMMU, 1);
> data = FIELD_DP32(data, CPUCFG1, IOCSR, 1);
> - data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f);
> - data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f);
> data = FIELD_DP32(data, CPUCFG1, UAL, 1);
> - data = FIELD_DP32(data, CPUCFG1, RI, 1);
> - data = FIELD_DP32(data, CPUCFG1, EP, 1);
> - data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
> - data = FIELD_DP32(data, CPUCFG1, HP, 1);
Sorry, this line should not be removed.
> data = FIELD_DP32(data, CPUCFG1, IOCSR_BRD, 1);
> env->cpucfg[1] = data;
>
> @@ -439,6 +427,45 @@ static void loongarch_la464_initfn(Object *obj)
> env->CSR_ASID = FIELD_DP64(0, CSR_ASID, ASIDBITS, 0xa);
> }
>
> +static void loongarch_la464_initfn(Object *obj)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> + CPULoongArchState *env = &cpu->env;
> +
> + loongarch_cpu_initfn_common(env);
> +
> + cpu->dtb_compatible = "loongarch,Loongson-3A5000";
> + env->cpucfg[0] = 0x14c010; /* PRID */
> +
> + uint32_t data = env->cpucfg[1];
> + data = FIELD_DP32(data, CPUCFG1, ARCH, 2); /* LA64 */
> + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); /* 48 bits */
> + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); /* 48 bits */
> + data = FIELD_DP32(data, CPUCFG1, RI, 1);
> + data = FIELD_DP32(data, CPUCFG1, EP, 1);
> + data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
> + env->cpucfg[1] = data;
> +}
> +
> +static void loongarch_la132_initfn(Object *obj)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> + CPULoongArchState *env = &cpu->env;
> +
> + loongarch_cpu_initfn_common(env);
> +
> + cpu->dtb_compatible = "loongarch,Loongson-1C103";
> +
> + uint32_t data = env->cpucfg[1];
> + data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
> + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
> + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
> + data = FIELD_DP32(data, CPUCFG1, RI, 0);
> + data = FIELD_DP32(data, CPUCFG1, EP, 0);
> + data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
> + env->cpucfg[1] = data;
> +}
> +
> static void loongarch_cpu_list_entry(gpointer data, gpointer user_data)
> {
> const char *typename = object_class_get_name(OBJECT_CLASS(data));
> @@ -784,5 +811,6 @@ static const TypeInfo loongarch32_cpu_type_infos[] = {
> .class_size = sizeof(LoongArchCPUClass),
> .class_init = loongarch32_cpu_class_init,
> },
> + DEFINE_LOONGARCH32_CPU_TYPE("la132", loongarch_la132_initfn),
> };
> DEFINE_TYPES(loongarch32_cpu_type_infos)
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 01/11] target/loongarch: Add macro to check current arch
2023-08-08 1:54 ` [PATCH v4 01/11] target/loongarch: Add macro to check current arch Jiajie Chen
@ 2023-08-08 17:01 ` Richard Henderson
2023-08-08 17:13 ` Jiajie Chen
2023-08-10 11:06 ` Philippe Mathieu-Daudé
1 sibling, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 17:01 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> Add macro to check if the current cpucfg[1].arch equals to 1(LA32) or
> 2(LA64).
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> target/loongarch/cpu.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index fa371ca8ba..bf0da8d5b4 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -132,6 +132,13 @@ FIELD(CPUCFG1, HP, 24, 1)
> FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
> FIELD(CPUCFG1, MSG_INT, 26, 1)
>
> +/* cpucfg[1].arch */
> +#define CPUCFG1_ARCH_LA32 1
> +#define CPUCFG1_ARCH_LA64 2
> +
> +#define LOONGARCH_CPUCFG_ARCH(env, mode) \
> + (FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_##mode)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
But in using this recall that 0 is a defined value for "simplified la32", so
!LOONGARCH_CPUCFG_ARCH(env, LA64)
may not in future equal
LOONGARCH_CPUCFG_ARCH(env, LA32)
it someone ever decides to implement this simplified version. (We emulate very small
embedded Arm cpus, so it's not out of the question that you may want to emulate the very
smallest LoongArch cpus.)
It might be easier to just define
static inline bool is_la64(CPULoongArch64 *env)
{
return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_LA64;
}
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 01/11] target/loongarch: Add macro to check current arch
2023-08-08 17:01 ` Richard Henderson
@ 2023-08-08 17:13 ` Jiajie Chen
2023-08-10 11:08 ` Philippe Mathieu-Daudé
0 siblings, 1 reply; 28+ messages in thread
From: Jiajie Chen @ 2023-08-08 17:13 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 2023/8/9 01:01, Richard Henderson wrote:
> On 8/7/23 18:54, Jiajie Chen wrote:
>> Add macro to check if the current cpucfg[1].arch equals to 1(LA32) or
>> 2(LA64).
>>
>> Signed-off-by: Jiajie Chen <c@jia.je>
>> ---
>> target/loongarch/cpu.h | 7 +++++++
>> 1 file changed, 7 insertions(+)
>>
>> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
>> index fa371ca8ba..bf0da8d5b4 100644
>> --- a/target/loongarch/cpu.h
>> +++ b/target/loongarch/cpu.h
>> @@ -132,6 +132,13 @@ FIELD(CPUCFG1, HP, 24, 1)
>> FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
>> FIELD(CPUCFG1, MSG_INT, 26, 1)
>> +/* cpucfg[1].arch */
>> +#define CPUCFG1_ARCH_LA32 1
>> +#define CPUCFG1_ARCH_LA64 2
>> +
>> +#define LOONGARCH_CPUCFG_ARCH(env, mode) \
>> + (FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_##mode)
>
> Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
>
> But in using this recall that 0 is a defined value for "simplified
> la32", so
>
> !LOONGARCH_CPUCFG_ARCH(env, LA64)
>
> may not in future equal
>
> LOONGARCH_CPUCFG_ARCH(env, LA32)
>
> it someone ever decides to implement this simplified version. (We
> emulate very small embedded Arm cpus, so it's not out of the question
> that you may want to emulate the very smallest LoongArch cpus.)
Yes, actually the LoongArch 32 Reduced (or "simplified la32") version is
my final aim because we are making embedded LoongArch32 Reduced CPUs on
FPGA for a competition, and supporting LoongArch 32 is the first step ahead.
>
> It might be easier to just define
>
> static inline bool is_la64(CPULoongArch64 *env)
> {
> return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) ==
> CPUCFG1_ARCH_LA64;
> }
Sure, I will use this way.
>
>
> r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 02/11] target/loongarch: Add new object class for loongarch32 cpus
2023-08-08 1:54 ` [PATCH v4 02/11] target/loongarch: Add new object class for loongarch32 cpus Jiajie Chen
@ 2023-08-08 18:19 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 18:19 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> Add object class for future loongarch32 cpus. It is derived from the
> loongarch64 object class.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> target/loongarch/cpu.c | 24 ++++++++++++++++++++++++
> target/loongarch/cpu.h | 11 +++++++++++
> 2 files changed, 35 insertions(+)
>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index ad93ecac92..3bd293d00a 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -732,6 +732,10 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
> #endif
> }
>
> +static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
> +{
> +}
> +
> #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
> { \
> .parent = TYPE_LOONGARCH_CPU, \
> @@ -754,3 +758,23 @@ static const TypeInfo loongarch_cpu_type_infos[] = {
> };
>
> DEFINE_TYPES(loongarch_cpu_type_infos)
> +
> +#define DEFINE_LOONGARCH32_CPU_TYPE(model, initfn) \
> + { \
> + .parent = TYPE_LOONGARCH32_CPU, \
> + .instance_init = initfn, \
> + .name = LOONGARCH_CPU_TYPE_NAME(model), \
> + }
> +
> +static const TypeInfo loongarch32_cpu_type_infos[] = {
> + {
> + .name = TYPE_LOONGARCH32_CPU,
> + .parent = TYPE_LOONGARCH_CPU,
> + .instance_size = sizeof(LoongArchCPU),
> +
> + .abstract = true,
> + .class_size = sizeof(LoongArchCPUClass),
> + .class_init = loongarch32_cpu_class_init,
> + },
> +};
You don't need to create a new array, you can put these into the existing
loongarch_cpu_type_infos[] like so:
static const TypeInfo loongarch_cpu_type_infos[] = {
{
.name = TYPE_LOONGARCH_CPU,
...
},
{
.name = TYPE_LOONGARCH32_CPU,
...
},
DEFINE_LOONGARCH_CPU_TYPE("la464", loongarch_la464_initfn),
DEFINE_LOONGARCH32_CPU_TYPE("la132", loongarch_la132_initfn),
};
> +#define TYPE_LOONGARCH32_CPU "loongarch32-cpu"
> +typedef struct LoongArch32CPUClass LoongArch32CPUClass;
> +DECLARE_CLASS_CHECKERS(LoongArch32CPUClass, LOONGARCH32_CPU,
> + TYPE_LOONGARCH32_CPU)
> +
> +struct LoongArch32CPUClass {
> + /*< private >*/
> + LoongArchCPUClass parent_class;
> + /*< public >*/
> +};
You don't need to declare another struct if it's just a wrapper.
If you do declare another struct, then you must actually use it in the .class_size
initializer.
Also, I've noticed two existing bugs:
(1) Missing alignment on fprs, which is required by tcg_gen_gvec_*:
typedef struct CPUArchState {
uint64_t gpr[32];
uint64_t pc;
- fpr_t fpr[32];
+ fpr_t fpr[32] QEMU_ALIGNED(16);
(2) Missing instance_align on the class:
.instance_align = __alignof(LoongArchCPU),
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 03/11] target/loongarch: Add GDB support for loongarch32 mode
2023-08-08 1:54 ` [PATCH v4 03/11] target/loongarch: Add GDB support for loongarch32 mode Jiajie Chen
@ 2023-08-08 18:34 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 18:34 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> GPRs and PC are 32-bit wide in loongarch32 mode.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> configs/targets/loongarch64-softmmu.mak | 2 +-
> gdb-xml/loongarch-base32.xml | 45 +++++++++++++++++++++++++
> target/loongarch/cpu.c | 10 +++++-
> target/loongarch/gdbstub.c | 32 ++++++++++++++----
> 4 files changed, 80 insertions(+), 9 deletions(-)
> create mode 100644 gdb-xml/loongarch-base32.xml
>
> diff --git a/configs/targets/loongarch64-softmmu.mak b/configs/targets/loongarch64-softmmu.mak
> index 9abc99056f..f23780fdd8 100644
> --- a/configs/targets/loongarch64-softmmu.mak
> +++ b/configs/targets/loongarch64-softmmu.mak
> @@ -1,5 +1,5 @@
> TARGET_ARCH=loongarch64
> TARGET_BASE_ARCH=loongarch
> TARGET_SUPPORTS_MTTCG=y
> -TARGET_XML_FILES= gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
> +TARGET_XML_FILES= gdb-xml/loongarch-base32.xml gdb-xml/loongarch-base64.xml gdb-xml/loongarch-fpu.xml
> TARGET_NEED_FDT=y
> diff --git a/gdb-xml/loongarch-base32.xml b/gdb-xml/loongarch-base32.xml
> new file mode 100644
> index 0000000000..af47bbd3da
> --- /dev/null
> +++ b/gdb-xml/loongarch-base32.xml
> @@ -0,0 +1,45 @@
> +<?xml version="1.0"?>
> +<!-- Copyright (C) 2022 Free Software Foundation, Inc.
> +
> + Copying and distribution of this file, with or without modification,
> + are permitted in any medium without royalty provided the copyright
> + notice and this notice are preserved. -->
> +
> +<!DOCTYPE feature SYSTEM "gdb-target.dtd">
> +<feature name="org.gnu.gdb.loongarch.base">
> + <reg name="r0" bitsize="32" type="uint32" group="general"/>
> + <reg name="r1" bitsize="32" type="code_ptr" group="general"/>
> + <reg name="r2" bitsize="32" type="data_ptr" group="general"/>
> + <reg name="r3" bitsize="32" type="data_ptr" group="general"/>
> + <reg name="r4" bitsize="32" type="uint32" group="general"/>
> + <reg name="r5" bitsize="32" type="uint32" group="general"/>
> + <reg name="r6" bitsize="32" type="uint32" group="general"/>
> + <reg name="r7" bitsize="32" type="uint32" group="general"/>
> + <reg name="r8" bitsize="32" type="uint32" group="general"/>
> + <reg name="r9" bitsize="32" type="uint32" group="general"/>
> + <reg name="r10" bitsize="32" type="uint32" group="general"/>
> + <reg name="r11" bitsize="32" type="uint32" group="general"/>
> + <reg name="r12" bitsize="32" type="uint32" group="general"/>
> + <reg name="r13" bitsize="32" type="uint32" group="general"/>
> + <reg name="r14" bitsize="32" type="uint32" group="general"/>
> + <reg name="r15" bitsize="32" type="uint32" group="general"/>
> + <reg name="r16" bitsize="32" type="uint32" group="general"/>
> + <reg name="r17" bitsize="32" type="uint32" group="general"/>
> + <reg name="r18" bitsize="32" type="uint32" group="general"/>
> + <reg name="r19" bitsize="32" type="uint32" group="general"/>
> + <reg name="r20" bitsize="32" type="uint32" group="general"/>
> + <reg name="r21" bitsize="32" type="uint32" group="general"/>
> + <reg name="r22" bitsize="32" type="data_ptr" group="general"/>
> + <reg name="r23" bitsize="32" type="uint32" group="general"/>
> + <reg name="r24" bitsize="32" type="uint32" group="general"/>
> + <reg name="r25" bitsize="32" type="uint32" group="general"/>
> + <reg name="r26" bitsize="32" type="uint32" group="general"/>
> + <reg name="r27" bitsize="32" type="uint32" group="general"/>
> + <reg name="r28" bitsize="32" type="uint32" group="general"/>
> + <reg name="r29" bitsize="32" type="uint32" group="general"/>
> + <reg name="r30" bitsize="32" type="uint32" group="general"/>
> + <reg name="r31" bitsize="32" type="uint32" group="general"/>
> + <reg name="orig_a0" bitsize="32" type="uint32" group="general"/>
> + <reg name="pc" bitsize="32" type="code_ptr" group="general"/>
> + <reg name="badv" bitsize="32" type="code_ptr" group="general"/>
> +</feature>
> diff --git a/target/loongarch/cpu.c b/target/loongarch/cpu.c
> index 3bd293d00a..13d4fccbd3 100644
> --- a/target/loongarch/cpu.c
> +++ b/target/loongarch/cpu.c
> @@ -694,7 +694,13 @@ static const struct SysemuCPUOps loongarch_sysemu_ops = {
>
> static gchar *loongarch_gdb_arch_name(CPUState *cs)
> {
> - return g_strdup("loongarch64");
> + LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> + CPULoongArchState *env = &cpu->env;
> + if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
> + return g_strdup("loongarch64");
> + } else {
> + return g_strdup("loongarch32");
> + }
> }
>
> static void loongarch_cpu_class_init(ObjectClass *c, void *data)
> @@ -734,6 +740,8 @@ static void loongarch_cpu_class_init(ObjectClass *c, void *data)
>
> static void loongarch32_cpu_class_init(ObjectClass *c, void *data)
> {
> + CPUClass *cc = CPU_CLASS(c);
> + cc->gdb_core_xml_file = "loongarch-base32.xml";
> }
>
> #define DEFINE_LOONGARCH_CPU_TYPE(model, initfn) \
> diff --git a/target/loongarch/gdbstub.c b/target/loongarch/gdbstub.c
> index 0752fff924..0dfd1c8bb9 100644
> --- a/target/loongarch/gdbstub.c
> +++ b/target/loongarch/gdbstub.c
> @@ -34,16 +34,25 @@ int loongarch_cpu_gdb_read_register(CPUState *cs, GByteArray *mem_buf, int n)
> {
> LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> CPULoongArchState *env = &cpu->env;
> + uint64_t val;
>
> if (0 <= n && n < 32) {
> - return gdb_get_regl(mem_buf, env->gpr[n]);
> + val = env->gpr[n];
> } else if (n == 32) {
> /* orig_a0 */
> - return gdb_get_regl(mem_buf, 0);
> + val = 0;
> } else if (n == 33) {
> - return gdb_get_regl(mem_buf, env->pc);
> + val = env->pc;
> } else if (n == 34) {
> - return gdb_get_regl(mem_buf, env->CSR_BADV);
> + val = env->CSR_BADV;
> + }
> +
> + if (0 <= n && n <= 34) {
> + if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
> + return gdb_get_reg64(mem_buf, val);
> + } else {
> + return gdb_get_reg32(mem_buf, val);
> + }
Is it an existing bug that BADV is readable...
> @@ -52,15 +61,24 @@ int loongarch_cpu_gdb_write_register(CPUState *cs, uint8_t *mem_buf, int n)
> {
> LoongArchCPU *cpu = LOONGARCH_CPU(cs);
> CPULoongArchState *env = &cpu->env;
> - target_ulong tmp = ldtul_p(mem_buf);
> + target_ulong tmp;
> + int read_length;
> int length = 0;
>
> + if (LOONGARCH_CPUCFG_ARCH(env, LA64)) {
> + tmp = ldq_p(mem_buf);
> + read_length = 8;
> + } else {
> + tmp = ldl_p(mem_buf);
> + read_length = 4;
> + }
> +
> if (0 <= n && n < 32) {
> env->gpr[n] = tmp;
> - length = sizeof(target_ulong);
> + length = read_length;
> } else if (n == 33) {
> env->pc = tmp;
> - length = sizeof(target_ulong);
> + length = read_length;
> }
... but not writable? I can't immediately see any reason why gdbstub should reject writes
to BADV.
But for this patch:
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry
2023-08-08 1:54 ` [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry Jiajie Chen
@ 2023-08-08 18:37 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 18:37 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> The TLB entry of LA32 lacks NR, NX and RPLV and they are hardwired to
> zero in LoongArch32.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> target/loongarch/cpu-csr.h | 9 +++++----
> target/loongarch/tlb_helper.c | 17 ++++++++++++-----
> 2 files changed, 17 insertions(+), 9 deletions(-)
Please retain Reviewed-by when given, as I did for v3. Anyway,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW
2023-08-08 1:54 ` [PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW Jiajie Chen
@ 2023-08-08 18:37 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 18:37 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> LA32 uses a different encoding for CSR.DMW and a new direct mapping
> mechanism.
>
> Signed-off-by: Jiajie Chen<c@jia.je>
> ---
> target/loongarch/cpu-csr.h | 7 +++----
> target/loongarch/tlb_helper.c | 26 +++++++++++++++++++++++---
> 2 files changed, 26 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN
2023-08-08 1:54 ` [PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN Jiajie Chen
@ 2023-08-08 18:38 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 18:38 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> VPPN of TLBEHI/TLBREHI is limited to 19 bits in LA32.
>
> Signed-off-by: Jiajie Chen<c@jia.je>
> ---
> target/loongarch/cpu-csr.h | 6 ++++--
> target/loongarch/tlb_helper.c | 23 ++++++++++++++++++-----
> 2 files changed, 22 insertions(+), 7 deletions(-)
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext
2023-08-08 1:54 ` [PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext Jiajie Chen
@ 2023-08-08 18:40 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 18:40 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> --- a/target/loongarch/translate.c
> +++ b/target/loongarch/translate.c
> @@ -119,6 +119,9 @@ static void loongarch_tr_init_disas_context(DisasContextBase *dcbase,
> ctx->vl = LSX_LEN;
> }
>
> + ctx->la32 = LOONGARCH_CPUCFG_ARCH(env, LA32);
> + ctx->va32 = (ctx->base.tb->flags & HW_FLAGS_VA32) != 0;
> +
> ctx->zero = tcg_constant_tl(0);
> }
>
> diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h
> index 7f60090580..828f1185d2 100644
> --- a/target/loongarch/translate.h
> +++ b/target/loongarch/translate.h
> @@ -33,6 +33,8 @@ typedef struct DisasContext {
> uint16_t plv;
> int vl; /* Vector length */
> TCGv zero;
> + bool la32; /* LoongArch32 mode */
Because if the LA32 Restricted (or simplified), let's make this la64.
Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode
2023-08-08 1:54 ` [PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode Jiajie Chen
@ 2023-08-08 18:48 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 18:48 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> -TRANS(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
> -TRANS(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
> -TRANS(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
> -TRANS(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
> +TRANS_64(addi_d, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_addi_tl)
> +TRANS_64(alsl_w, gen_rrr_sa, EXT_NONE, EXT_SIGN, gen_alsl)
> +TRANS_64(alsl_wu, gen_rrr_sa, EXT_NONE, EXT_ZERO, gen_alsl)
> +TRANS_64(alsl_d, gen_rrr_sa, EXT_NONE, EXT_NONE, gen_alsl)
alsl.w is in LA32, according to the table 2 on page 15.
> +/* for LoongArch64-only instructions */
> +#define TRANS_64(NAME, FUNC, ...) \
> + static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \
> + { \
> + if (ctx->la32) { \
> + return false; \
> + } \
> + return FUNC(ctx, a, __VA_ARGS__); \
> + }
With the change suggested for patch 7, this becomes
return ctx->la64 && FUNC(...)
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode
2023-08-08 1:54 ` [PATCH v4 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode Jiajie Chen
@ 2023-08-08 19:08 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 19:08 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> When running in VA32 mode(LA32 or VA32L[1-3] matching PLV), virtual
> address is truncated to 32 bits before address mapping.
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> target/loongarch/cpu.h | 6 +++++-
> target/loongarch/insn_trans/trans_atomic.c.inc | 1 +
> target/loongarch/insn_trans/trans_fmemory.c.inc | 8 ++++++++
> target/loongarch/insn_trans/trans_lsx.c.inc | 6 ++++++
> target/loongarch/insn_trans/trans_memory.c.inc | 10 ++++++++++
> target/loongarch/translate.c | 10 ++++++++++
> 6 files changed, 40 insertions(+), 1 deletion(-)
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index 69589f0aef..9ad5fcc494 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -457,7 +457,11 @@ static inline void cpu_get_tb_cpu_state(CPULoongArchState *env, vaddr *pc,
> va32 = 1;
> }
>
> - *pc = env->pc;
> + if (va32) {
> + *pc = (uint32_t)env->pc;
> + } else {
> + *pc = env->pc;
> + }
This is not wrong, but it might be better to zero-extend when assigning to env->pc. There
are other consumers of env->pc, and we are not updating all of them.
> --- a/target/loongarch/insn_trans/trans_memory.c.inc
> +++ b/target/loongarch/insn_trans/trans_memory.c.inc
> @@ -13,6 +13,7 @@ static bool gen_load(DisasContext *ctx, arg_rr_i *a, MemOp mop)
> tcg_gen_addi_tl(temp, addr, a->imm);
> addr = temp;
> }
> + addr = va32_address(ctx, addr);
I did say that you should use a common helper and a single temp.
This is using two temps: one here and one in va32_address.
I suggest:
static TCGv make_address_x(DisasContext *ctx, TCGv base, TCGv addend)
{
TCGv temp = NULL;
if (addend || ctx->va32) {
temp = tcg_temp_new();
}
if (addend) {
tcg_gen_add_tl(temp, base, addend);
base = temp;
}
if (ctx->va32) {
tcg_gen_ext32u_tl(temp, base);
base = temp;
}
return base;
}
static TCGv make_address_i(DisasContext *ctx, TCGv base, target_long ofs)
{
TCGv addend = ofs ? tcg_constant_tl(ofs) : NULL;
return make_address_x(ctx, base, addend);
}
So that gen_load uses
addr = make_address_i(ctx, addr, a->imm);
and gen_loadx uses
addr = make_address_x(ctx, src1, src2);
and gen_am uses
addr = make_address_i(ctx, addr, 0);
and so on for all of the others.
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 10/11] target/loongarch: Sign extend results in VA32 mode
2023-08-08 1:54 ` [PATCH v4 10/11] target/loongarch: Sign extend results " Jiajie Chen
@ 2023-08-08 19:12 ` Richard Henderson
0 siblings, 0 replies; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 19:12 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> --- a/target/loongarch/translate.c
> +++ b/target/loongarch/translate.c
> @@ -218,6 +218,19 @@ static TCGv va32_address(DisasContext *ctx, TCGv addr)
> return addr;
> }
>
> +static uint64_t sign_extend32(uint64_t data)
> +{
> + return (data & 0x7FFFFFFF) - (data & 0x80000000);
> +}
While correct, this is just (int32_t)data.
You can fold that into the only user.
> +
> +static uint64_t va32_result(DisasContext *ctx, uint64_t addr)
> +{
> + if (ctx->va32) {
> + addr = sign_extend32(addr);
> + }
> + return addr;
> +}
I would call this make_address_pc to match make_address_{i,x}.
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132
2023-08-08 1:54 ` [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132 Jiajie Chen
2023-08-08 1:59 ` Jiajie Chen
@ 2023-08-08 19:26 ` Richard Henderson
2023-08-09 7:31 ` Jiajie Chen
1 sibling, 1 reply; 28+ messages in thread
From: Richard Henderson @ 2023-08-08 19:26 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/7/23 18:54, Jiajie Chen wrote:
> +static void loongarch_la464_initfn(Object *obj)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> + CPULoongArchState *env = &cpu->env;
> +
> + loongarch_cpu_initfn_common(env);
> +
> + cpu->dtb_compatible = "loongarch,Loongson-3A5000";
> + env->cpucfg[0] = 0x14c010; /* PRID */
> +
> + uint32_t data = env->cpucfg[1];
> + data = FIELD_DP32(data, CPUCFG1, ARCH, 2); /* LA64 */
> + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); /* 48 bits */
> + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); /* 48 bits */
> + data = FIELD_DP32(data, CPUCFG1, RI, 1);
> + data = FIELD_DP32(data, CPUCFG1, EP, 1);
> + data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
> + env->cpucfg[1] = data;
> +}
> +
> +static void loongarch_la132_initfn(Object *obj)
> +{
> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
> + CPULoongArchState *env = &cpu->env;
> +
> + loongarch_cpu_initfn_common(env);
> +
> + cpu->dtb_compatible = "loongarch,Loongson-1C103";
> +
> + uint32_t data = env->cpucfg[1];
> + data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
> + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
> + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
> + data = FIELD_DP32(data, CPUCFG1, RI, 0);
> + data = FIELD_DP32(data, CPUCFG1, EP, 0);
> + data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
> + env->cpucfg[1] = data;
> +}
The use of the loongarch_cpu_initfn_common function is not going to scale.
Compare the set of *_initfn in target/arm/tcg/cpu32.c
In general, you want to copy data in bulk from the processor manual, so that the reviewer
can simply read through the table and see that the code is correct, without having to
check between multiple functions to see that the combination is correct.
For our existing la464, that table is Table 54 in the 3A5000 manual.
Is there a public specification for the la132? I could not find one in
https://www.loongson.cn/EN/product/, but perhaps that's just the english view.
r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132
2023-08-08 19:26 ` Richard Henderson
@ 2023-08-09 7:31 ` Jiajie Chen
0 siblings, 0 replies; 28+ messages in thread
From: Jiajie Chen @ 2023-08-09 7:31 UTC (permalink / raw)
To: Richard Henderson, qemu-devel; +Cc: yijun, shenjinyang, gaosong, i.qemu
On 2023/8/9 03:26, Richard Henderson wrote:
> On 8/7/23 18:54, Jiajie Chen wrote:
>> +static void loongarch_la464_initfn(Object *obj)
>> +{
>> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
>> + CPULoongArchState *env = &cpu->env;
>> +
>> + loongarch_cpu_initfn_common(env);
>> +
>> + cpu->dtb_compatible = "loongarch,Loongson-3A5000";
>> + env->cpucfg[0] = 0x14c010; /* PRID */
>> +
>> + uint32_t data = env->cpucfg[1];
>> + data = FIELD_DP32(data, CPUCFG1, ARCH, 2); /* LA64 */
>> + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x2f); /* 48 bits */
>> + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x2f); /* 48 bits */
>> + data = FIELD_DP32(data, CPUCFG1, RI, 1);
>> + data = FIELD_DP32(data, CPUCFG1, EP, 1);
>> + data = FIELD_DP32(data, CPUCFG1, RPLV, 1);
>> + env->cpucfg[1] = data;
>> +}
>> +
>> +static void loongarch_la132_initfn(Object *obj)
>> +{
>> + LoongArchCPU *cpu = LOONGARCH_CPU(obj);
>> + CPULoongArchState *env = &cpu->env;
>> +
>> + loongarch_cpu_initfn_common(env);
>> +
>> + cpu->dtb_compatible = "loongarch,Loongson-1C103";
>> +
>> + uint32_t data = env->cpucfg[1];
>> + data = FIELD_DP32(data, CPUCFG1, ARCH, 1); /* LA32 */
>> + data = FIELD_DP32(data, CPUCFG1, PALEN, 0x1f); /* 32 bits */
>> + data = FIELD_DP32(data, CPUCFG1, VALEN, 0x1f); /* 32 bits */
>> + data = FIELD_DP32(data, CPUCFG1, RI, 0);
>> + data = FIELD_DP32(data, CPUCFG1, EP, 0);
>> + data = FIELD_DP32(data, CPUCFG1, RPLV, 0);
>> + env->cpucfg[1] = data;
>> +}
>
> The use of the loongarch_cpu_initfn_common function is not going to
> scale.
> Compare the set of *_initfn in target/arm/tcg/cpu32.c
>
> In general, you want to copy data in bulk from the processor manual,
> so that the reviewer can simply read through the table and see that
> the code is correct, without having to check between multiple
> functions to see that the combination is correct.
>
> For our existing la464, that table is Table 54 in the 3A5000 manual.
>
> Is there a public specification for the la132? I could not find one
> in https://www.loongson.cn/EN/product/, but perhaps that's just the
> english view.
There seems no, even from the chinese view.
>
>
> r~
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 01/11] target/loongarch: Add macro to check current arch
2023-08-08 1:54 ` [PATCH v4 01/11] target/loongarch: Add macro to check current arch Jiajie Chen
2023-08-08 17:01 ` Richard Henderson
@ 2023-08-10 11:06 ` Philippe Mathieu-Daudé
1 sibling, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-10 11:06 UTC (permalink / raw)
To: Jiajie Chen, qemu-devel
Cc: richard.henderson, yijun, shenjinyang, gaosong, i.qemu
On 8/8/23 03:54, Jiajie Chen wrote:
> Add macro to check if the current cpucfg[1].arch equals to 1(LA32) or
> 2(LA64).
>
> Signed-off-by: Jiajie Chen <c@jia.je>
> ---
> target/loongarch/cpu.h | 7 +++++++
> 1 file changed, 7 insertions(+)
>
> diff --git a/target/loongarch/cpu.h b/target/loongarch/cpu.h
> index fa371ca8ba..bf0da8d5b4 100644
> --- a/target/loongarch/cpu.h
> +++ b/target/loongarch/cpu.h
> @@ -132,6 +132,13 @@ FIELD(CPUCFG1, HP, 24, 1)
> FIELD(CPUCFG1, IOCSR_BRD, 25, 1)
> FIELD(CPUCFG1, MSG_INT, 26, 1)
>
> +/* cpucfg[1].arch */
> +#define CPUCFG1_ARCH_LA32 1
> +#define CPUCFG1_ARCH_LA64 2
> +
> +#define LOONGARCH_CPUCFG_ARCH(env, mode) \
> + (FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) == CPUCFG1_ARCH_##mode)
The 'LOONGARCH_CPUCFG_ARCH()' macro name is misleading. If you want
to return a boolean, maybe rename as CHECK(). But clearer would be
a function (taking an enum CPUCFG1_ARCH_LAxx argument).
> /* cpucfg[2] bits */
> FIELD(CPUCFG2, FP, 0, 1)
> FIELD(CPUCFG2, FP_SP, 1, 1)
^ permalink raw reply [flat|nested] 28+ messages in thread
* Re: [PATCH v4 01/11] target/loongarch: Add macro to check current arch
2023-08-08 17:13 ` Jiajie Chen
@ 2023-08-10 11:08 ` Philippe Mathieu-Daudé
0 siblings, 0 replies; 28+ messages in thread
From: Philippe Mathieu-Daudé @ 2023-08-10 11:08 UTC (permalink / raw)
To: Jiajie Chen, Richard Henderson, qemu-devel
Cc: yijun, shenjinyang, gaosong, i.qemu
On 8/8/23 19:13, Jiajie Chen wrote:
>
> On 2023/8/9 01:01, Richard Henderson wrote:
>> On 8/7/23 18:54, Jiajie Chen wrote:
>>> Add macro to check if the current cpucfg[1].arch equals to 1(LA32) or
>>> 2(LA64).
>>>
>>> Signed-off-by: Jiajie Chen <c@jia.je>
>>> ---
>>> target/loongarch/cpu.h | 7 +++++++
>>> 1 file changed, 7 insertions(+)
>> It might be easier to just define
>>
>> static inline bool is_la64(CPULoongArch64 *env)
>> {
>> return FIELD_EX32(env->cpucfg[1], CPUCFG1, ARCH) ==
>> CPUCFG1_ARCH_LA64;
>> }
Ah, drop my other suggestion (Richard's way is simpler).
> Sure, I will use this way.
^ permalink raw reply [flat|nested] 28+ messages in thread
end of thread, other threads:[~2023-08-10 11:08 UTC | newest]
Thread overview: 28+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
2023-08-08 1:54 [PATCH v4 00/11] Add la32 & va32 mode for loongarch64-softmmu Jiajie Chen
2023-08-08 1:54 ` [PATCH v4 01/11] target/loongarch: Add macro to check current arch Jiajie Chen
2023-08-08 17:01 ` Richard Henderson
2023-08-08 17:13 ` Jiajie Chen
2023-08-10 11:08 ` Philippe Mathieu-Daudé
2023-08-10 11:06 ` Philippe Mathieu-Daudé
2023-08-08 1:54 ` [PATCH v4 02/11] target/loongarch: Add new object class for loongarch32 cpus Jiajie Chen
2023-08-08 18:19 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 03/11] target/loongarch: Add GDB support for loongarch32 mode Jiajie Chen
2023-08-08 18:34 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 04/11] target/loongarch: Support LoongArch32 TLB entry Jiajie Chen
2023-08-08 18:37 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 05/11] target/loongarch: Support LoongArch32 DMW Jiajie Chen
2023-08-08 18:37 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 06/11] target/loongarch: Support LoongArch32 VPPN Jiajie Chen
2023-08-08 18:38 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 07/11] target/loongarch: Add LA32 & VA32 to DisasContext Jiajie Chen
2023-08-08 18:40 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 08/11] target/loongarch: Reject la64-only instructions in la32 mode Jiajie Chen
2023-08-08 18:48 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 09/11] target/loongarch: Truncate high 32 bits of address in VA32 mode Jiajie Chen
2023-08-08 19:08 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 10/11] target/loongarch: Sign extend results " Jiajie Chen
2023-08-08 19:12 ` Richard Henderson
2023-08-08 1:54 ` [PATCH v4 11/11] target/loongarch: Add loongarch32 cpu la132 Jiajie Chen
2023-08-08 1:59 ` Jiajie Chen
2023-08-08 19:26 ` Richard Henderson
2023-08-09 7:31 ` Jiajie Chen
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