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Fri, 12 Dec 2025 08:55:20 -0800 (PST) Received: from [10.229.62.227] ([187.217.227.247]) by smtp.gmail.com with ESMTPSA id 46e09a7af769-7cadb1d1089sm3737305a34.6.2025.12.12.08.55.19 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 12 Dec 2025 08:55:20 -0800 (PST) Message-ID: Date: Fri, 12 Dec 2025 10:55:17 -0600 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH-for-11.0 v3 17/22] target/mips: Inline cpu_ld/st_mmuidx_ra() calls in memory helpers To: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= , qemu-devel@nongnu.org Cc: qemu-s390x@nongnu.org, qemu-riscv@nongnu.org, qemu-ppc@nongnu.org, Aurelien Jarno , Jiaxun Yang , Aleksandar Rikalo References: <20251126202200.23100-1-philmd@linaro.org> <20251126202200.23100-18-philmd@linaro.org> From: Richard Henderson Content-Language: en-US In-Reply-To: <20251126202200.23100-18-philmd@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2607:f8b0:4864:20::330; envelope-from=richard.henderson@linaro.org; helo=mail-ot1-x330.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/26/25 14:21, Philippe Mathieu-Daudé wrote: > In preparation of removing the cpu_ld*_mmuidx_ra() and > cpu_st*_mmuidx_ra() calls, inline them. Expand MO_TE to > mo_endian_env(env). > > Signed-off-by: Philippe Mathieu-Daudé > --- > target/mips/tcg/ldst_helper.c | 49 +++++++++++++++++++---------------- > 1 file changed, 27 insertions(+), 22 deletions(-) > > diff --git a/target/mips/tcg/ldst_helper.c b/target/mips/tcg/ldst_helper.c > index f3652034afa..716b60e3a39 100644 > --- a/target/mips/tcg/ldst_helper.c > +++ b/target/mips/tcg/ldst_helper.c > @@ -237,8 +237,10 @@ void helper_sdr(CPUMIPSState *env, target_ulong arg1, target_ulong arg2, > static const int multiple_regs[] = { 16, 17, 18, 19, 20, 21, 22, 23, 30 }; > > void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, > - uint32_t mem_idx) > + uint32_t mmu_idx) > { > + MemOp op = mo_endian_env(env) | MO_UL | MO_UNALN; > + MemOpIdx oi = make_memop_idx(op, mmu_idx); > target_ulong base_reglist = reglist & 0xf; > target_ulong do_r31 = reglist & 0x10; > > @@ -247,20 +249,22 @@ void helper_lwm(CPUMIPSState *env, target_ulong addr, target_ulong reglist, > > for (i = 0; i < base_reglist; i++) { > env->active_tc.gpr[multiple_regs[i]] = > - (target_long)cpu_ldl_mmuidx_ra(env, addr, mem_idx, GETPC()); > + (target_long)cpu_ldl_mmu(env, addr, oi, GETPC()); While this is a faithful expansion of cpu_ldl_mmuidx_ra, v5 micromips requires alignment and v6 micromips does not. You may be better served passing the whole MemOpIdx down with MO_ALIGN vs MO_UNALN. Or, indeed, dropping the helper entirely and implementing the function inline -- this maxes out at 10 load/stores after all. r~