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[2.142.241.104]) by smtp.gmail.com with ESMTPSA id l2sm5945244wmi.1.2021.11.10.06.40.54 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 10 Nov 2021 06:40:55 -0800 (PST) Subject: Re: [PATCH v2 05/14] target/riscv: Calculate address according to XLEN To: LIU Zhiwei , qemu-devel@nongnu.org, qemu-riscv@nongnu.org, Alexey Baturo References: <20211110070452.48539-1-zhiwei_liu@c-sky.com> <20211110070452.48539-6-zhiwei_liu@c-sky.com> <7dace3b5-1320-20b3-703c-bbdf7e745fb9@linaro.org> From: Richard Henderson Message-ID: Date: Wed, 10 Nov 2021 15:40:52 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 8bit X-Host-Lookup-Failed: Reverse DNS lookup failed for 2a00:1450:4864:20::32c (failed) Received-SPF: pass client-ip=2a00:1450:4864:20::32c; envelope-from=richard.henderson@linaro.org; helo=mail-wm1-x32c.google.com X-Spam_score_int: -25 X-Spam_score: -2.6 X-Spam_bar: -- X-Spam_report: (-2.6 / 5.0 requ) BAYES_00=-1.9, DKIM_INVALID=0.1, DKIM_SIGNED=0.1, NICE_REPLY_A=-1.678, PDS_HP_HELO_NORDNS=0.001, RCVD_IN_DNSWL_NONE=-0.0001, RDNS_NONE=0.793, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: palmer@dabbelt.com, bin.meng@windriver.com, Alistair.Francis@wdc.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/10/21 2:44 PM, LIU Zhiwei wrote: >> I suspect the extend should come before the pointer mask and not after, but this is is a >> weakness in the current RVJ spec that it does not specify how the extension interacts >> with UXL.  (The reverse ordering would allow a 64-bit os to place a 32-bit application >> at a base address above 4gb, which could allow address separation without paging enabled.) > > Agree. Should we adjust currently, or just add a TODO comment here? Let's add a todo comment for sure. >> I do think we should merge gen_pm_adjust_address into this function so that we only >> create one new temporary. > > I think custom instructions will be added in the future. And possibly there will be  some > custom load/store instructions. > If we merge gen_pm_adjust_address,  we may have to split it once again at that time. I don't think so. We're simply having one function to compute a canonical address from a register plus offset plus mods. Also, patch 10 combines pm-mask with zero-extension, so we shouldn't need to do both here. The checks should be combined like tcg_gen_addi_tl(addr, src1, imm); if (ctx->pm_enabled) { tcg_gen_and_tl(addr, addr, pm_mask); tcg_gen_or_tl(addr, addr, pm_base); } else if (get_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } and could possibly be extended to if (ctx->pm_mask_enabled) { tcg_gen_and_tl(addr, addr, pm_mask); } else if (get_xl(ctx) == MXL_RV32) { tcg_gen_ext32u_tl(addr, addr); } if (ctx->pm_base_enabled) { tcg_gen_or_tl(addr, addr, pm_base); } with one more bit in TB_FLAGS, e.g. if (env->cur_pm_mask < (xl == MVL_RV32 ? UINT32_MAX : UINT64_MAX)) { flags = FIELD_DP32(flags, TB_FLAGS, PM_MASK_ENABLED, 1); } if (env->cur_pm_base != 0) { flags = FIELD_DP32(flags, TB_FLAGS, PM_BASE_ENABLED, 1); } r~