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[74.87.59.234]) by smtp.gmail.com with ESMTPSA id a20-20020aa780d4000000b0058d54960eccsm11936550pfn.151.2023.02.15.10.22.44 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Feb 2023 10:22:45 -0800 (PST) Message-ID: Date: Wed, 15 Feb 2023 08:22:39 -1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH 1/4] util/cacheflush: fix illegal instruction on windows-arm64 Content-Language: en-US To: Pierrick Bouvier , Peter Maydell Cc: qemu-devel@nongnu.org, sw@weilnetz.de, kkostiuk@redhat.com, clg@kaod.org, alex.bennee@linaro.org References: <20230213161352.17199-1-pierrick.bouvier@linaro.org> <20230213161352.17199-2-pierrick.bouvier@linaro.org> <01e0e1f1-96ea-2294-f8ea-8a36320021e5@linaro.org> From: Richard Henderson In-Reply-To: <01e0e1f1-96ea-2294-f8ea-8a36320021e5@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::52f; envelope-from=richard.henderson@linaro.org; helo=mail-pg1-x52f.google.com X-Spam_score_int: -23 X-Spam_score: -2.4 X-Spam_bar: -- X-Spam_report: (-2.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.257, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/15/23 02:49, Pierrick Bouvier wrote: > I'm not an expert on this area, but I imagine that booting a full VM will force TCG to > emit code at the same address twice (after having generated enough translated blocks), > which shows that generic flush_idcache_range works. Is that reasoning correct? > > Do you think we still need a specialized version for windows-arm64? No, I don't think so. It would be ideal if we were able to read CTR_EL0, because we make use of the IDC field, but 0 is a safe default. r~