Re: [PATCH 1/2] target/mips: Implement Loongson CSR instructions

["Philippe Mathieu-Daudé" <philmd@linaro.org>]

On 10/7/23 22:11, Philippe Mathieu-Daudé wrote:
> On 21/5/23 23:48, Jiaxun Yang wrote:
>> Loongson introduced CSR instructions since 3A4000, which looks
>> similar to IOCSR and CPUCFG instructions we seen in LoongArch.
>>
>> Unfortunately we don't have much document about those instructions,
>> bit fields of CPUCFG instructions and IOCSR registers can be found
>> at 3A4000's user manual, while instruction encodings can be found
>> at arch/mips/include/asm/mach-loongson64/loongson_regs.h from
>> Linux Kernel.
>>
>> Our predefined CPUCFG bits are differ from actual 3A4000, since
>> we can't emulate all CPUCFG features present in 3A4000 for now,
>> we just enable bits for what we have in TCG.
>>
>> Signed-off-by: Jiaxun Yang <jiaxun.yang@flygoat.com>
>> ---
>>   target/mips/cpu-defs.c.inc           |  9 ++++
>>   target/mips/cpu.c                    |  8 ++++
>>   target/mips/cpu.h                    | 40 ++++++++++++++++
>>   target/mips/helper.h                 |  4 ++
>>   target/mips/internal.h               |  2 +
>>   target/mips/tcg/lcsr.decode          | 17 +++++++
>>   target/mips/tcg/lcsr_translate.c     | 69 ++++++++++++++++++++++++++++
>>   target/mips/tcg/meson.build          |  2 +
>>   target/mips/tcg/op_helper.c          | 16 +++++++
>>   target/mips/tcg/sysemu/lcsr_helper.c | 45 ++++++++++++++++++
>>   target/mips/tcg/sysemu/meson.build   |  4 ++
>>   target/mips/tcg/sysemu_helper.h.inc  |  8 ++++
>>   target/mips/tcg/translate.c          |  3 ++
>>   target/mips/tcg/translate.h          |  7 +++
>>   14 files changed, 234 insertions(+)
>>   create mode 100644 target/mips/tcg/lcsr.decode
>>   create mode 100644 target/mips/tcg/lcsr_translate.c
>>   create mode 100644 target/mips/tcg/sysemu/lcsr_helper.c
> 
> 
>> @@ -1162,6 +1192,10 @@ typedef struct CPUArchState {
>>       QEMUTimer *timer; /* Internal timer */
>>       Clock *count_clock; /* CP0_Count clock */
>>       target_ulong exception_base; /* ExceptionBase input to the core */
>> +
>> +    /* Loongson IOCSR memory */
>> +    AddressSpace address_space_iocsr;
>> +    MemoryRegion system_iocsr;
>>   } CPUMIPSState;
> 
> Guarding to avoid on user emulation:
> 
> ../target/mips/cpu.h:1198:22: error: field ‘as’ has incomplete type
>   1198 |         AddressSpace as;
>        |                      ^~
> ../target/mips/cpu.h:1199:22: error: field ‘mr’ has incomplete type
>   1199 |         MemoryRegion mr;
>        |                      ^~
> 

and:

../../target/mips/cpu.c: In function ‘mips_cpu_initfn’:
../../target/mips/cpu.c:513:9: error: implicit declaration of function 
‘memory_region_init_io’ [-Werror=implicit-function-declaration]
   513 |         memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL,
       |         ^~~~~~~~~~~~~~~~~~~~~
../../target/mips/cpu.c:513:9: error: nested extern declaration of 
‘memory_region_init_io’ [-Werror=nested-externs]
../../target/mips/cpu.c:513:35: error: ‘CPUMIPSState’ {aka ‘struct 
CPUArchState’} has no member named ‘iocsr’
   513 |         memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL,
       |                                   ^~
../../target/mips/cpu.c:515:9: error: implicit declaration of function 
‘address_space_init’ [-Werror=implicit-function-declaration]
   515 |         address_space_init(&env->iocsr.as,
       |         ^~~~~~~~~~~~~~~~~~
../../target/mips/cpu.c:515:9: error: nested extern declaration of 
‘address_space_init’ [-Werror=nested-externs]
../../target/mips/cpu.c:515:32: error: ‘CPUMIPSState’ {aka ‘struct 
CPUArchState’} has no member named ‘iocsr’
   515 |         address_space_init(&env->iocsr.as,
       |                                ^~
../../target/mips/cpu.c:516:33: error: ‘CPUMIPSState’ {aka ‘struct 
CPUArchState’} has no member named ‘iocsr’
   516 |                             &env->iocsr.mr, "IOCSR");
       |                                 ^~
cc1: all warnings being treated as errors

:(