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[176.184.47.225]) by smtp.gmail.com with ESMTPSA id u19-20020a05600c00d300b003fc02e8ea68sm8741427wmm.13.2023.07.10.14.34.12 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 10 Jul 2023 14:34:13 -0700 (PDT) Message-ID: Date: Mon, 10 Jul 2023 23:34:10 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.13.0 Subject: Re: [PATCH 1/2] target/mips: Implement Loongson CSR instructions Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= To: Jiaxun Yang , qemu-devel@nongnu.org Cc: yangxiaojuan@loongson.cn, gaosong@loongson.cn, chenhuacai@kernel.org References: <20230521214832.20145-1-jiaxun.yang@flygoat.com> <20230521214832.20145-2-jiaxun.yang@flygoat.com> In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::335; envelope-from=philmd@linaro.org; helo=mail-wm1-x335.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.101, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 10/7/23 22:11, Philippe Mathieu-Daudé wrote: > On 21/5/23 23:48, Jiaxun Yang wrote: >> Loongson introduced CSR instructions since 3A4000, which looks >> similar to IOCSR and CPUCFG instructions we seen in LoongArch. >> >> Unfortunately we don't have much document about those instructions, >> bit fields of CPUCFG instructions and IOCSR registers can be found >> at 3A4000's user manual, while instruction encodings can be found >> at arch/mips/include/asm/mach-loongson64/loongson_regs.h from >> Linux Kernel. >> >> Our predefined CPUCFG bits are differ from actual 3A4000, since >> we can't emulate all CPUCFG features present in 3A4000 for now, >> we just enable bits for what we have in TCG. >> >> Signed-off-by: Jiaxun Yang >> --- >>   target/mips/cpu-defs.c.inc           |  9 ++++ >>   target/mips/cpu.c                    |  8 ++++ >>   target/mips/cpu.h                    | 40 ++++++++++++++++ >>   target/mips/helper.h                 |  4 ++ >>   target/mips/internal.h               |  2 + >>   target/mips/tcg/lcsr.decode          | 17 +++++++ >>   target/mips/tcg/lcsr_translate.c     | 69 ++++++++++++++++++++++++++++ >>   target/mips/tcg/meson.build          |  2 + >>   target/mips/tcg/op_helper.c          | 16 +++++++ >>   target/mips/tcg/sysemu/lcsr_helper.c | 45 ++++++++++++++++++ >>   target/mips/tcg/sysemu/meson.build   |  4 ++ >>   target/mips/tcg/sysemu_helper.h.inc  |  8 ++++ >>   target/mips/tcg/translate.c          |  3 ++ >>   target/mips/tcg/translate.h          |  7 +++ >>   14 files changed, 234 insertions(+) >>   create mode 100644 target/mips/tcg/lcsr.decode >>   create mode 100644 target/mips/tcg/lcsr_translate.c >>   create mode 100644 target/mips/tcg/sysemu/lcsr_helper.c > > >> @@ -1162,6 +1192,10 @@ typedef struct CPUArchState { >>       QEMUTimer *timer; /* Internal timer */ >>       Clock *count_clock; /* CP0_Count clock */ >>       target_ulong exception_base; /* ExceptionBase input to the core */ >> + >> +    /* Loongson IOCSR memory */ >> +    AddressSpace address_space_iocsr; >> +    MemoryRegion system_iocsr; >>   } CPUMIPSState; > > Guarding to avoid on user emulation: > > ../target/mips/cpu.h:1198:22: error: field ‘as’ has incomplete type >  1198 |         AddressSpace as; >       |                      ^~ > ../target/mips/cpu.h:1199:22: error: field ‘mr’ has incomplete type >  1199 |         MemoryRegion mr; >       |                      ^~ > and: ../../target/mips/cpu.c: In function ‘mips_cpu_initfn’: ../../target/mips/cpu.c:513:9: error: implicit declaration of function ‘memory_region_init_io’ [-Werror=implicit-function-declaration] 513 | memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL, | ^~~~~~~~~~~~~~~~~~~~~ ../../target/mips/cpu.c:513:9: error: nested extern declaration of ‘memory_region_init_io’ [-Werror=nested-externs] ../../target/mips/cpu.c:513:35: error: ‘CPUMIPSState’ {aka ‘struct CPUArchState’} has no member named ‘iocsr’ 513 | memory_region_init_io(&env->iocsr.mr, OBJECT(cpu), NULL, | ^~ ../../target/mips/cpu.c:515:9: error: implicit declaration of function ‘address_space_init’ [-Werror=implicit-function-declaration] 515 | address_space_init(&env->iocsr.as, | ^~~~~~~~~~~~~~~~~~ ../../target/mips/cpu.c:515:9: error: nested extern declaration of ‘address_space_init’ [-Werror=nested-externs] ../../target/mips/cpu.c:515:32: error: ‘CPUMIPSState’ {aka ‘struct CPUArchState’} has no member named ‘iocsr’ 515 | address_space_init(&env->iocsr.as, | ^~ ../../target/mips/cpu.c:516:33: error: ‘CPUMIPSState’ {aka ‘struct CPUArchState’} has no member named ‘iocsr’ 516 | &env->iocsr.mr, "IOCSR"); | ^~ cc1: all warnings being treated as errors :(