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[216.180.64.156]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-7246a9d67c6sm1518872b3a.192.2024.11.14.10.08.27 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 14 Nov 2024 10:08:27 -0800 (PST) Message-ID: Date: Thu, 14 Nov 2024 10:08:27 -0800 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 20/54] include/exec/tlb-common: Move CPUTLBEntryFull from hw/core/cpu.h Content-Language: en-US To: Richard Henderson , qemu-devel@nongnu.org References: <20241114160131.48616-1-richard.henderson@linaro.org> <20241114160131.48616-21-richard.henderson@linaro.org> From: Pierrick Bouvier In-Reply-To: <20241114160131.48616-21-richard.henderson@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::62c; envelope-from=pierrick.bouvier@linaro.org; helo=mail-pl1-x62c.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 11/14/24 08:00, Richard Henderson wrote: > CPUTLBEntryFull structures are no longer directly included within > the CPUState structure. Move the structure definition out of cpu.h > to reduce visibility. > > Signed-off-by: Richard Henderson > --- > include/exec/tlb-common.h | 63 +++++++++++++++++++++++++++++++++++++++ > include/hw/core/cpu.h | 63 --------------------------------------- > 2 files changed, 63 insertions(+), 63 deletions(-) > > diff --git a/include/exec/tlb-common.h b/include/exec/tlb-common.h > index dc5a5faa0b..300f9fae67 100644 > --- a/include/exec/tlb-common.h > +++ b/include/exec/tlb-common.h > @@ -53,4 +53,67 @@ typedef struct CPUTLBDescFast { > CPUTLBEntry *table; > } CPUTLBDescFast QEMU_ALIGNED(2 * sizeof(void *)); > > +/* > + * The full TLB entry, which is not accessed by generated TCG code, > + * so the layout is not as critical as that of CPUTLBEntry. This is > + * also why we don't want to combine the two structs. > + */ > +struct CPUTLBEntryFull { > + /* > + * @xlat_section contains: > + * - in the lower TARGET_PAGE_BITS, a physical section number > + * - with the lower TARGET_PAGE_BITS masked off, an offset which > + * must be added to the virtual address to obtain: > + * + the ram_addr_t of the target RAM (if the physical section > + * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) > + * + the offset within the target MemoryRegion (otherwise) > + */ > + hwaddr xlat_section; > + > + /* > + * @phys_addr contains the physical address in the address space > + * given by cpu_asidx_from_attrs(cpu, @attrs). > + */ > + hwaddr phys_addr; > + > + /* @attrs contains the memory transaction attributes for the page. */ > + MemTxAttrs attrs; > + > + /* @prot contains the complete protections for the page. */ > + uint8_t prot; > + > + /* @lg_page_size contains the log2 of the page size. */ > + uint8_t lg_page_size; > + > + /* Additional tlb flags requested by tlb_fill. */ > + uint8_t tlb_fill_flags; > + > + /* > + * Additional tlb flags for use by the slow path. If non-zero, > + * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. > + */ > + uint8_t slow_flags[MMU_ACCESS_COUNT]; > + > + /* > + * Allow target-specific additions to this structure. > + * This may be used to cache items from the guest cpu > + * page tables for later use by the implementation. > + */ > + union { > + /* > + * Cache the attrs and shareability fields from the page table entry. > + * > + * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. > + * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. > + * For shareability and guarded, as in the SH and GP fields respectively > + * of the VMSAv8-64 PTEs. > + */ > + struct { > + uint8_t pte_attrs; > + uint8_t shareability; > + bool guarded; > + } arm; > + } extra; > +}; > + > #endif /* EXEC_TLB_COMMON_H */ > diff --git a/include/hw/core/cpu.h b/include/hw/core/cpu.h > index 8eda0574b2..4364ddb1db 100644 > --- a/include/hw/core/cpu.h > +++ b/include/hw/core/cpu.h > @@ -201,69 +201,6 @@ struct CPUClass { > */ > #define NB_MMU_MODES 16 > > -/* > - * The full TLB entry, which is not accessed by generated TCG code, > - * so the layout is not as critical as that of CPUTLBEntry. This is > - * also why we don't want to combine the two structs. > - */ > -struct CPUTLBEntryFull { > - /* > - * @xlat_section contains: > - * - in the lower TARGET_PAGE_BITS, a physical section number > - * - with the lower TARGET_PAGE_BITS masked off, an offset which > - * must be added to the virtual address to obtain: > - * + the ram_addr_t of the target RAM (if the physical section > - * number is PHYS_SECTION_NOTDIRTY or PHYS_SECTION_ROM) > - * + the offset within the target MemoryRegion (otherwise) > - */ > - hwaddr xlat_section; > - > - /* > - * @phys_addr contains the physical address in the address space > - * given by cpu_asidx_from_attrs(cpu, @attrs). > - */ > - hwaddr phys_addr; > - > - /* @attrs contains the memory transaction attributes for the page. */ > - MemTxAttrs attrs; > - > - /* @prot contains the complete protections for the page. */ > - uint8_t prot; > - > - /* @lg_page_size contains the log2 of the page size. */ > - uint8_t lg_page_size; > - > - /* Additional tlb flags requested by tlb_fill. */ > - uint8_t tlb_fill_flags; > - > - /* > - * Additional tlb flags for use by the slow path. If non-zero, > - * the corresponding CPUTLBEntry comparator must have TLB_FORCE_SLOW. > - */ > - uint8_t slow_flags[MMU_ACCESS_COUNT]; > - > - /* > - * Allow target-specific additions to this structure. > - * This may be used to cache items from the guest cpu > - * page tables for later use by the implementation. > - */ > - union { > - /* > - * Cache the attrs and shareability fields from the page table entry. > - * > - * For ARMMMUIdx_Stage2*, pte_attrs is the S2 descriptor bits [5:2]. > - * Otherwise, pte_attrs is the same as the MAIR_EL1 8-bit format. > - * For shareability and guarded, as in the SH and GP fields respectively > - * of the VMSAv8-64 PTEs. > - */ > - struct { > - uint8_t pte_attrs; > - uint8_t shareability; > - bool guarded; > - } arm; > - } extra; > -}; > - > /* > * Data elements that are per MMU mode, minus the bits accessed by > * the TCG fast path. Reviewed-by: Pierrick Bouvier