Re: [PATCH v3 02/16] target/arm: Create gen_gvec_{u,s}{rshr,rsra}

[Richard Henderson <richard.henderson@linaro.org>]

On 5/12/20 6:46 AM, Peter Maydell wrote:
> +void gen_gvec_srshr(unsigned vece, uint32_t rd_ofs, uint32_t rm_ofs,
> +                    int64_t shift, uint32_t opr_sz, uint32_t max_sz)
> +{
> +    static const TCGOpcode vecop_list[] = {
> +        INDEX_op_shri_vec, INDEX_op_sari_vec, INDEX_op_add_vec, 0
> +    };
> 
> Is there documentation somewhere of which vector operations don't
> need to be listed in the vecop list? Here gen_srshr_vec() also
> uses 'dupi_vec' and 'and_vec', which aren't listed, presumably
> because we guarantee them to be implemented? (Hopefully we don't
> encounter a future host vector architecture which breaks that
> assumption :-))

Yes, though perhaps not perfectly easy to find: it's at the top of tcg-op-vec.c.

Correct, that the logicals and mov/dupi etc are mandatory and should not be
listed.  Moreover, I assert that they are *not* listed, so we get a
CONFIG_DEBUG_TCG check of this list both positive and negative.

I'm going to hope that no future architecture is so irregular as to not
implement logicals.  ;-)  Or even be as irregular as Intel.

>> I think the VRSRA case needs the same "shift = -shift" as VRSHR.
> 
> With this bug fixed,
> Reviewed-by: Peter Maydell <peter.maydell@linaro.org>

Thanks, fixed.


r~