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[176.184.39.152]) by smtp.gmail.com with ESMTPSA id g13-20020adfe40d000000b002f8d402b191sm5196364wrm.112.2023.04.21.14.31.46 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Fri, 21 Apr 2023 14:31:47 -0700 (PDT) Message-ID: Date: Fri, 21 Apr 2023 23:31:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.10.0 Subject: Re: [PATCH] hw/riscv: virt: Enable booting M-mode or S-mode FW from pflash0 Content-Language: en-US To: Andrea Bolognani , Heinrich Schuchardt Cc: Sunil V L , qemu-devel@nongnu.org, Palmer Dabbelt , Alistair Francis , Bin Meng , Weiwei Li , Daniel Henrique Barboza , Liu Zhiwei , qemu-riscv@nongnu.org References: <20230421043353.125701-1-sunilvl@ventanamicro.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::32b; envelope-from=philmd@linaro.org; helo=mail-wm1-x32b.google.com X-Spam_score_int: -53 X-Spam_score: -5.4 X-Spam_bar: ----- X-Spam_report: (-5.4 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-3.297, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 21/4/23 18:48, Andrea Bolognani wrote: > On Fri, Apr 21, 2023 at 04:36:15PM +0200, Heinrich Schuchardt wrote: >> On 4/21/23 06:33, Sunil V L wrote: >>> Currently, virt machine supports two pflash instances each with >>> 32MB size. However, the first pflash is always assumed to >>> contain M-mode firmware and reset vector is set to this if >>> enabled. Hence, for S-mode payloads like EDK2, only one pflash >>> instance is available for use. This means both code and NV variables >>> of EDK2 will need to use the same pflash. >>> >>> The OS distros keep the EDK2 FW code as readonly. When non-volatile >>> variables also need to share the same pflash, it is not possible >>> to keep it as readonly since variables need write access. >>> >>> To resolve this issue, the code and NV variables need to be separated. >>> But in that case we need an extra flash. Hence, modify the convention >>> such that pflash0 will contain the M-mode FW only when "-bios none" >>> option is used. Otherwise, pflash0 will contain the S-mode payload FW. >>> This enables both pflash instances available for EDK2 use. >>> >>> Example usage: >>> 1) pflash0 containing M-mode FW >>> qemu-system-riscv64 -bios none -pflash -machine virt >>> or >>> qemu-system-riscv64 -bios none \ >>> -drive file=,if=pflash,format=raw,unit=0 -machine virt >>> >>> 2) pflash0 containing S-mode payload like EDK2 >>> qemu-system-riscv64 -pflash -pflash -machine virt >>> or >>> qemu-system-riscv64 -bios \ >>> -pflash \ >>> -pflash \ >>> -machine virt >>> or >>> qemu-system-riscv64 -bios \ >>> -drive file=,if=pflash,format=raw,unit=0,readonly=on \ >>> -drive file=,if=pflash,format=raw,unit=1 \ >>> -machine virt >>> >>> Signed-off-by: Sunil V L >>> Reported-by: Heinrich Schuchardt >> >> QEMU 7.2 (and possibly 8.0 to be released) contains the old behavior. >> >> Changed use of command line parameters should depend on the version of >> the virt machine, i.e. virt-7.2 should use the old behavior and virt as >> alias for virt-8.0 should use the new behavior. Please, have a look at >> the option handling in hw/arm/virt.c and macro DEFINE_VIRT_MACHINE(). > > I would normally agree with you, but note that RISC-V doesn't have > versioned machine types yet, so this kind of breakage is not > necessarily unexpected. > > From libvirt's point of view, being able to detect whether the new > behavior is implemented by looking for some machine type property > would be enough to handle the transition smoothly. That would of > course not help people running QEMU directly. > > For what it's worth, this change seems to go in the right direction > by making things similar to other architectures (x86, Arm) so I'd > love to see it happen. Unfortunately another arch that followed the bad example of using a R/W device for the CODE region and not a simple ROM.