From: Richard Henderson <richard.henderson@linaro.org>
To: Nicholas Piggin <npiggin@gmail.com>,
Daniel Henrique Barboza <danielhb413@gmail.com>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, qemu-stable@nongnu.org
Subject: Re: [PATCH 4/4] target/ppc: Rework store conditional to avoid branch
Date: Sun, 4 Jun 2023 09:22:35 -0700 [thread overview]
Message-ID: <bcd3a4ce-37c2-af3e-0d66-bac4e9bd7eac@linaro.org> (raw)
In-Reply-To: <20230604102858.148584-4-npiggin@gmail.com>
On 6/4/23 03:28, Nicholas Piggin wrote:
> Rework store conditional to avoid a branch in the success case.
> Change some of the variable names and layout while here so
> gen_conditional_store more closely matches gen_stqcx_.
>
> Signed-off-by: Nicholas Piggin <npiggin@gmail.com>
> ---
> target/ppc/translate.c | 65 ++++++++++++++++++++----------------------
> 1 file changed, 31 insertions(+), 34 deletions(-)
>
> diff --git a/target/ppc/translate.c b/target/ppc/translate.c
> index 77e1c5abb6..cf99e961f7 100644
> --- a/target/ppc/translate.c
> +++ b/target/ppc/translate.c
> @@ -3812,31 +3812,32 @@ static void gen_stdat(DisasContext *ctx)
>
> static void gen_conditional_store(DisasContext *ctx, MemOp memop)
> {
> - TCGLabel *l1 = gen_new_label();
> - TCGLabel *l2 = gen_new_label();
> - TCGv t0 = tcg_temp_new();
> - int reg = rS(ctx->opcode);
> + TCGLabel *lfail;
> + TCGv EA;
> + TCGv cr0;
> + TCGv t0;
> + int rs = rS(ctx->opcode);
>
> + lfail = gen_new_label();
> + EA = tcg_temp_new();
> + cr0 = tcg_temp_new();
> + t0 = tcg_temp_new();
> +
> + tcg_gen_mov_tl(cr0, cpu_so);
> gen_set_access_type(ctx, ACCESS_RES);
> - gen_addr_reg_index(ctx, t0);
> - tcg_gen_brcond_tl(TCG_COND_NE, t0, cpu_reserve, l1);
> - tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, memop_size(memop), l1);
> + gen_addr_reg_index(ctx, EA);
> + tcg_gen_brcond_tl(TCG_COND_NE, EA, cpu_reserve, lfail);
> + tcg_gen_brcondi_tl(TCG_COND_NE, cpu_reserve_size, memop_size(memop), lfail);
>
> - t0 = tcg_temp_new();
> tcg_gen_atomic_cmpxchg_tl(t0, cpu_reserve, cpu_reserve_val,
> - cpu_gpr[reg], ctx->mem_idx,
> - DEF_MEMOP(memop) | MO_ALIGN);
> + cpu_gpr[rs], ctx->mem_idx,
> + memop | MO_ALIGN);
Lost DEF_MEMOP here. Otherwise,
Reviewed-by: Richard Henderson <richard.henderson@linaro.org>
r~
next prev parent reply other threads:[~2023-06-04 16:23 UTC|newest]
Thread overview: 15+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-06-04 10:28 [PATCH 1/4] target/ppc: Fix lqarx to set cpu_reserve Nicholas Piggin
2023-06-04 10:28 ` [PATCH 2/4] target/ppc: Ensure stcx size matches larx Nicholas Piggin
2023-06-04 16:58 ` Richard Henderson
2023-06-05 6:27 ` Nicholas Piggin
2023-06-19 15:48 ` Richard Henderson
2023-06-19 15:55 ` Peter Maydell
2023-06-19 17:02 ` Richard Henderson
2023-06-19 17:14 ` Peter Maydell
2023-06-20 3:39 ` Nicholas Piggin
2023-06-04 10:28 ` [PATCH 3/4] target/ppc: Remove larx/stcx. memory barrier semantics Nicholas Piggin
2023-06-04 16:12 ` Richard Henderson
2023-06-04 10:28 ` [PATCH 4/4] target/ppc: Rework store conditional to avoid branch Nicholas Piggin
2023-06-04 16:22 ` Richard Henderson [this message]
2023-06-04 16:05 ` [PATCH 1/4] target/ppc: Fix lqarx to set cpu_reserve Richard Henderson
2023-06-05 2:33 ` Nicholas Piggin
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