From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: pbonzini@redhat.com, palmer@dabbelt.com,
Alistair.Francis@wdc.com, laurent@vivier.eu, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, Jim Shu <jim.shu@sifive.com>,
Andy Chiu <andy.chiu@sifive.com>
Subject: Re: [PATCH v3 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp
Date: Wed, 7 Aug 2024 10:56:12 +1000 [thread overview]
Message-ID: <bd2f7f31-966e-4bec-a4be-8c030d1ac4a7@linaro.org> (raw)
In-Reply-To: <20240807000652.1417776-4-debug@rivosinc.com>
On 8/7/24 10:06, Deepak Gupta wrote:
> +/* enum for branch tracking state in cpu/hart */
> +typedef enum {
> + NO_LP_EXPECTED = 0,
> + LP_EXPECTED = 1,
> +} cfi_elp;
I know this is language is in the spec, but would it make more sense to use
bool elp_expected;
?
If not, Coding Style requires CamelCase for typedefs.
r~
next prev parent reply other threads:[~2024-08-07 0:56 UTC|newest]
Thread overview: 59+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-07 0:06 [PATCH v3 00/20] riscv support for control flow integrity extensions Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 01/20] accel/tcg: restrict assert on icount_enabled to qemu-system Deepak Gupta
2024-08-07 0:48 ` Richard Henderson
2024-08-07 18:45 ` Deepak Gupta
2024-08-12 17:41 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 02/20] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 03/20] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-07 0:56 ` Richard Henderson [this message]
2024-08-07 18:46 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 04/20] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-07 1:06 ` Richard Henderson
2024-08-07 20:11 ` Deepak Gupta
2024-08-07 22:40 ` Richard Henderson
2024-08-07 22:58 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 05/20] target/riscv: additional code information for sw check Deepak Gupta
2024-08-07 1:11 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 06/20] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-07 1:23 ` Richard Henderson
2024-08-07 20:15 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 07/20] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-07 2:01 ` Richard Henderson
2024-08-07 2:04 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 08/20] disas/riscv: enabled `lpad` disassembly Deepak Gupta
2024-08-07 2:06 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 09/20] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 10/20] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-07 2:11 ` Richard Henderson
2024-08-07 2:12 ` Richard Henderson
2024-08-07 20:21 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 11/20] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-07 2:13 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 12/20] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-07 2:39 ` Richard Henderson
2024-08-07 2:56 ` Richard Henderson
2024-08-07 21:25 ` Deepak Gupta
2024-08-07 20:35 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 13/20] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-07 2:40 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 14/20] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-07 3:19 ` Richard Henderson
2024-08-09 18:55 ` Deepak Gupta
2024-08-11 22:23 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 15/20] target/riscv: shadow stack mmu index for shadow stack instructions Deepak Gupta
2024-08-07 2:43 ` Richard Henderson
2024-08-07 21:23 ` Deepak Gupta
2024-08-07 22:57 ` Richard Henderson
2024-08-07 23:13 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 16/20] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-07 3:24 ` Richard Henderson
2024-08-07 0:06 ` [PATCH v3 17/20] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 18/20] target/riscv: add trace-hooks for each case of sw-check exception Deepak Gupta
2024-08-07 3:27 ` Richard Henderson
2024-08-07 20:52 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 19/20] linux-user: permit RISC-V CFI dynamic entry in VDSO Deepak Gupta
2024-08-07 3:36 ` Richard Henderson
2024-08-07 20:53 ` Deepak Gupta
2024-08-07 0:06 ` [PATCH v3 20/20] linux-user: Add RISC-V zicfilp support " Deepak Gupta
2024-08-07 3:41 ` Richard Henderson
2024-08-07 21:00 ` Deepak Gupta
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=bd2f7f31-966e-4bec-a4be-8c030d1ac4a7@linaro.org \
--to=richard.henderson@linaro.org \
--cc=Alistair.Francis@wdc.com \
--cc=andy.chiu@sifive.com \
--cc=bmeng.cn@gmail.com \
--cc=dbarboza@ventanamicro.com \
--cc=debug@rivosinc.com \
--cc=jim.shu@sifive.com \
--cc=laurent@vivier.eu \
--cc=liwei1518@gmail.com \
--cc=palmer@dabbelt.com \
--cc=pbonzini@redhat.com \
--cc=qemu-devel@nongnu.org \
--cc=qemu-riscv@nongnu.org \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).