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From: "Cédric Le Goater" <clg@kaod.org>
To: David Gibson <david@gibson.dropbear.id.au>
Cc: qemu-ppc@nongnu.org, qemu-devel@nongnu.org, Greg Kurz <groug@kaod.org>
Subject: Re: [Qemu-devel] [PATCH v5 1/3] spapr: introduce a fixed IRQ number space
Date: Mon, 30 Jul 2018 11:05:58 +0200	[thread overview]
Message-ID: <bd62d2e5-eab6-84c5-c110-dfd93768885d@kaod.org> (raw)
In-Reply-To: <20180727035611.GG3694@umbus.fritz.box>

On 07/27/2018 05:56 AM, David Gibson wrote:
> On Thu, Jul 26, 2018 at 03:37:21PM +0200, Cédric Le Goater wrote:
>> This proposal introduces a new IRQ number space layout using static
>> numbers for all devices, depending on a device index, and a bitmap
>> allocator for the MSI IRQ numbers which are negotiated by the guest at
>> runtime.
>>
>> As the VIO device model does not have a device index but a "reg"
>> property, we introduce a formula to compute an IRQ number from a "reg"
>> value. It should minimize most of the collisions.
>>
>> The previous layout is kept in pre-3.1 machines raising the
>> 'legacy_irq_allocation' machine class flag.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> 
> One nit left..
> 
> [snip]
>> +static inline uint32_t spapr_vio_reg_to_irq(uint32_t reg)
>> +{
>> +    uint32_t irq;
>> +
>> +    if (reg >= SPAPR_VIO_REG_BASE) {
>> +        /*
>> +         * VIO device register values when allocated by QEMU. For
>> +         * these, we simply mask the high bits to fit the overall
>> +         * range: [0x00 - 0xff].
>> +         *
>> +         * The nvram VIO device (reg=0x71000000) is a static device of
>> +         * the pseries machine and so is always allocated by QEMU. Its
>> +         * IRQ number is 0x0.
>> +         */
>> +        irq = reg & 0xff;
>> +
>> +    } else if (reg >= 0x30000000) {
>> +        /*
>> +         * VIO tty devices register values, when allocated by livirt,
>> +         * are mapped in range [0xf0 - 0xff], gives us a maximum of 16
>> +         * vtys.
>> +         */
>> +        irq = 0xf0 | ((reg >> 12) & 0xf);
>> +
>> +    } else {
>> +        /*
>> +         * Other VIO devices register values, when allocated by
>> +         * livirt, are mapped in range [0x00 - 0xef].
>> +         */
>> +        irq = (reg >> 12) & 0xef;
> 
> This mask doesn't do what you intend - it will map 0x10 to 0, for
> example.  You could use % 0xf0, but actually you might as well just
> use & 0xff.  Yes, it could collide with the vty devices, but either
> way you can still have collisions if you try hard enough.  And, either
> way, they'll get detected later.
> 


David,

Shall I resend a v6 with this fix or should I wait for the patch adding 
3.1. I could also send a 3.1 pseries machine also if you prefer.

Thanks,

C.

  parent reply	other threads:[~2018-07-30  9:06 UTC|newest]

Thread overview: 12+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2018-07-26 13:37 [Qemu-devel] [PATCH v5 0/3] spapr: introduce a fixed IRQ number space and an IRQ controller backend Cédric Le Goater
2018-07-26 13:37 ` [Qemu-devel] [PATCH v5 1/3] spapr: introduce a fixed IRQ number space Cédric Le Goater
2018-07-27  3:56   ` David Gibson
2018-07-27  6:56     ` Cédric Le Goater
2018-07-30  9:05     ` Cédric Le Goater [this message]
2018-07-30  9:39       ` David Gibson
2018-07-26 13:37 ` [Qemu-devel] [PATCH v5 2/3] spapr: introduce a IRQ controller backend to the machine Cédric Le Goater
2018-07-27  5:16   ` David Gibson
2018-07-27  7:04     ` Cédric Le Goater
2018-07-30  4:05       ` David Gibson
2018-07-30 13:57     ` Cédric Le Goater
2018-07-26 13:37 ` [Qemu-devel] [PATCH v5 3/3] spapr: increase the size of the IRQ number space Cédric Le Goater

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