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From: "Philippe Mathieu-Daudé" <philmd@linaro.org>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
	qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com,
	liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com,
	palmer@dabbelt.com, "Dr. David Alan Gilbert" <dave@treblig.org>,
	Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
Subject: Re: [PATCH] hmp-cmds-target, target/riscv: add 'info register'
Date: Mon, 30 Jun 2025 18:00:25 +0200	[thread overview]
Message-ID: <be01b414-f30f-4ca5-a515-94a60187e8e6@linaro.org> (raw)
In-Reply-To: <20250630132228.1276838-1-dbarboza@ventanamicro.com>

Hi Daniel,

On 30/6/25 15:22, Daniel Henrique Barboza wrote:
> The RISC-V target has *a lot* of CPU registers, with more registers
> being added along the way when new extensions are added. In this world,
> 'info registers' will throw a wall of text that can be annoying to deal
> with when the user wants to verify the value of just a couple of
> registers.
> 
> Add a new 'info register' HMP command that prints a specific register.
> The semantics, and implementation, is similar to what 'info registers'
> already does, i.e. '-a' will print a register for all VCPUs and it's
> possible to print a reg for a specific VCPU.
> 
> A RISC-V implementation is included via riscv_cpu_dump_register().
> 
> Here's an example:
> 
> Welcome to Buildroot
> buildroot login: QEMU 10.0.50 monitor - type 'help' for more information
> (qemu) info register mstatus
> 
> CPU#0
>   mstatus  0000000a000000a0
> (qemu) info register mstatus -a
> 
> CPU#0
>   mstatus  0000000a000000a0
> 
> CPU#1
>   mstatus  0000000a000000a0
> (qemu)
> 
> The API is introduced as TARGET_RISCV only.
> 
> Cc: Dr. David Alan Gilbert <dave@treblig.org>
> Cc: Marcel Apfelbaum <marcel.apfelbaum@gmail.com>
> Cc: Philippe Mathieu-Daudé <philmd@linaro.org>
> Signed-off-by: Daniel Henrique Barboza <dbarboza@ventanamicro.com>
> ---
>   hmp-commands-info.hx         | 17 +++++++++++++
>   hw/core/cpu-common.c         |  8 ++++++
>   include/hw/core/cpu.h        | 11 +++++++++
>   include/monitor/hmp-target.h |  1 +
>   monitor/hmp-cmds-target.c    | 30 ++++++++++++++++++++++
>   target/riscv/cpu.c           | 48 ++++++++++++++++++++++++++++++++++++
>   6 files changed, 115 insertions(+)
> 
> diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx
> index 639a450ee5..f3561e4a02 100644
> --- a/hmp-commands-info.hx
> +++ b/hmp-commands-info.hx
> @@ -113,6 +113,23 @@ SRST
>       Show the cpu registers.
>   ERST
>   
> +#if defined(TARGET_RISCV)

Just make this command available for all targets, displaying
"No such register" or better when no handler registered.

> +    {
> +        .name       = "register",
> +        .args_type  = "register:s,cpustate_all:-a,vcpu:i?",
> +        .params     = "[register|-a|vcpu]",
> +        .help       = "show a cpu register (-a: show the register value for all cpus;"
> +                      " vcpu: specific vCPU to query; show the current CPU's register if"
> +                      " no vcpu is specified)",

I'd invert the default behavior: dump for all vcpus except if a specific
one is specified.

I wonder about a 'info register -h' do list all register names available.

> +        .cmd        = hmp_info_register,
> +    },
> +
> +SRST
> +  ``info register``
> +    Show a cpu register.
> +ERST
> +#endif

Regards,

Phil.


  reply	other threads:[~2025-06-30 16:01 UTC|newest]

Thread overview: 6+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-06-30 13:22 [PATCH] hmp-cmds-target, target/riscv: add 'info register' Daniel Henrique Barboza
2025-06-30 16:00 ` Philippe Mathieu-Daudé [this message]
2025-06-30 17:46   ` Daniel Henrique Barboza
2025-07-01  0:07 ` Dr. David Alan Gilbert
2025-07-01 22:05   ` Daniel Henrique Barboza
2025-07-02  0:24     ` Dr. David Alan Gilbert

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