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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-453822c6b9fsm169425725e9.0.2025.06.30.09.00.25 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 30 Jun 2025 09:00:26 -0700 (PDT) Message-ID: Date: Mon, 30 Jun 2025 18:00:25 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH] hmp-cmds-target, target/riscv: add 'info register' To: Daniel Henrique Barboza , qemu-devel@nongnu.org Cc: qemu-riscv@nongnu.org, alistair.francis@wdc.com, liwei1518@gmail.com, zhiwei_liu@linux.alibaba.com, palmer@dabbelt.com, "Dr. David Alan Gilbert" , Marcel Apfelbaum References: <20250630132228.1276838-1-dbarboza@ventanamicro.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250630132228.1276838-1-dbarboza@ventanamicro.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::42a; envelope-from=philmd@linaro.org; helo=mail-wr1-x42a.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Daniel, On 30/6/25 15:22, Daniel Henrique Barboza wrote: > The RISC-V target has *a lot* of CPU registers, with more registers > being added along the way when new extensions are added. In this world, > 'info registers' will throw a wall of text that can be annoying to deal > with when the user wants to verify the value of just a couple of > registers. > > Add a new 'info register' HMP command that prints a specific register. > The semantics, and implementation, is similar to what 'info registers' > already does, i.e. '-a' will print a register for all VCPUs and it's > possible to print a reg for a specific VCPU. > > A RISC-V implementation is included via riscv_cpu_dump_register(). > > Here's an example: > > Welcome to Buildroot > buildroot login: QEMU 10.0.50 monitor - type 'help' for more information > (qemu) info register mstatus > > CPU#0 > mstatus 0000000a000000a0 > (qemu) info register mstatus -a > > CPU#0 > mstatus 0000000a000000a0 > > CPU#1 > mstatus 0000000a000000a0 > (qemu) > > The API is introduced as TARGET_RISCV only. > > Cc: Dr. David Alan Gilbert > Cc: Marcel Apfelbaum > Cc: Philippe Mathieu-Daudé > Signed-off-by: Daniel Henrique Barboza > --- > hmp-commands-info.hx | 17 +++++++++++++ > hw/core/cpu-common.c | 8 ++++++ > include/hw/core/cpu.h | 11 +++++++++ > include/monitor/hmp-target.h | 1 + > monitor/hmp-cmds-target.c | 30 ++++++++++++++++++++++ > target/riscv/cpu.c | 48 ++++++++++++++++++++++++++++++++++++ > 6 files changed, 115 insertions(+) > > diff --git a/hmp-commands-info.hx b/hmp-commands-info.hx > index 639a450ee5..f3561e4a02 100644 > --- a/hmp-commands-info.hx > +++ b/hmp-commands-info.hx > @@ -113,6 +113,23 @@ SRST > Show the cpu registers. > ERST > > +#if defined(TARGET_RISCV) Just make this command available for all targets, displaying "No such register" or better when no handler registered. > + { > + .name = "register", > + .args_type = "register:s,cpustate_all:-a,vcpu:i?", > + .params = "[register|-a|vcpu]", > + .help = "show a cpu register (-a: show the register value for all cpus;" > + " vcpu: specific vCPU to query; show the current CPU's register if" > + " no vcpu is specified)", I'd invert the default behavior: dump for all vcpus except if a specific one is specified. I wonder about a 'info register -h' do list all register names available. > + .cmd = hmp_info_register, > + }, > + > +SRST > + ``info register`` > + Show a cpu register. > +ERST > +#endif Regards, Phil.