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[128.178.122.40]) by smtp.gmail.com with ESMTPSA id p4-20020a50cd84000000b004fc24b4a283sm1498075edi.40.2023.03.15.02.27.09 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Wed, 15 Mar 2023 02:27:10 -0700 (PDT) Message-ID: Date: Wed, 15 Mar 2023 10:27:08 +0100 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.7.1 Subject: Re: [PATCH for-8.0] hw/char/cadence_uart: Fix guards on invalid BRGR/BDIV settings Content-Language: en-US To: Peter Maydell , qemu-arm@nongnu.org, qemu-devel@nongnu.org Cc: "Edgar E. Iglesias" , Alistair Francis , cyruscyliu@gmail.com References: <20230314170804.1196232-1-peter.maydell@linaro.org> From: Qiang Liu In-Reply-To: <20230314170804.1196232-1-peter.maydell@linaro.org> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::536; envelope-from=cyruscyliu@gmail.com; helo=mail-ed1-x536.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, FREEMAIL_FROM=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 3/14/23 6:08 PM, Peter Maydell wrote: > The cadence UART attempts to avoid allowing the guset to set invalid > baud rate register values in the uart_write() function. However it > does the "mask to the size of the register field" and "check for > invalid values" in the wrong order, which means that a malicious > guest can get a bogus value into the register by setting also some > high bits in the value, and cause QEMU to crash by division-by-zero. > > Do the mask before the bounds check instead of afterwards. > > Resolves: https://gitlab.com/qemu-project/qemu/-/issues/1493 > Signed-off-by: Peter Maydell > --- > hw/char/cadence_uart.c | 6 ++++-- > 1 file changed, 4 insertions(+), 2 deletions(-) > > diff --git a/hw/char/cadence_uart.c b/hw/char/cadence_uart.c > index c069a30842e..807e3985419 100644 > --- a/hw/char/cadence_uart.c > +++ b/hw/char/cadence_uart.c > @@ -450,13 +450,15 @@ static MemTxResult uart_write(void *opaque, hwaddr offset, > } > break; > case R_BRGR: /* Baud rate generator */ > + value &= 0xffff; > if (value >= 0x01) { > - s->r[offset] = value & 0xFFFF; > + s->r[offset] = value; > } > break; > case R_BDIV: /* Baud rate divider */ > + value &= 0xff; > if (value >= 0x04) { > - s->r[offset] = value & 0xFF; > + s->r[offset] = value; > } > break; > default: Tested on my side. Tested-by: Qiang Liu