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[172.254.253.57]) by smtp.gmail.com with ESMTPSA id f23sm10376180qtq.40.2021.11.01.11.04.05 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 01 Nov 2021 11:04:05 -0700 (PDT) Subject: Re: [PATCH v2] hvf: arm: Ignore cache operations on MMIO To: Peter Maydell References: <20211026071241.74889-1-agraf@csgraf.de> <13a13852-4fb4-a0f8-6740-354c8054aed1@linaro.org> From: Richard Henderson Message-ID: Date: Mon, 1 Nov 2021 14:04:03 -0400 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.13.0 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8; format=flowed Content-Language: en-US Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::735; envelope-from=richard.henderson@linaro.org; helo=mail-qk1-x735.google.com X-Spam_score_int: -31 X-Spam_score: -3.2 X-Spam_bar: --- X-Spam_report: (-3.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-1.14, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: kettenis@openbsd.org, =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= , Cameron Esfahani , qemu-devel@nongnu.org, Roman Bolshakov , Alexander Graf , Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 11/1/21 1:55 PM, Peter Maydell wrote: > On Tue, 26 Oct 2021 at 17:22, Richard Henderson > wrote: >> >> On 10/26/21 12:12 AM, Alexander Graf wrote: >>> + if (cm) { >>> + /* We don't cache MMIO regions */ >>> + advance_pc = true; >>> + break; >>> + } >>> + >>> assert(isv); >> >> The assert should come first. If the "iss valid" bit is not set, then nothing else in the >> word is defined. > > No, ISV only indicates that ISS[23:14] is valid; ISS[13:0] (including CM) > are valid regardless. (The distinction is that the bits which might or > might not be valid are the ones which encode information about the insn > necessary to possibly emulate it, like the data access size and the > source/destination register; the always-present ones are the ones that > have always been reported for data aborts -- AArch32 DFSR has a CM bit, > for instance.) Thanks, that clears up some of my confusion here and a bit further downthread. r~