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[174.21.72.5]) by smtp.gmail.com with ESMTPSA id w23-20020a17090a461700b002a04eef22c5sm9006219pjg.44.2024.04.16.10.57.42 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 16 Apr 2024 10:57:43 -0700 (PDT) Message-ID: Date: Tue, 16 Apr 2024 10:57:40 -0700 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH 2/8] target/ppc: Make divw[u] handler method decodetree compatible. To: Chinmay Rath , qemu-ppc@nongnu.org Cc: qemu-devel@nongnu.org, npiggin@gmail.com, danielhb413@gmail.com, harshpb@linux.ibm.com References: <20240416063927.99428-1-rathc@linux.ibm.com> <20240416063927.99428-3-rathc@linux.ibm.com> Content-Language: en-US From: Richard Henderson In-Reply-To: <20240416063927.99428-3-rathc@linux.ibm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2607:f8b0:4864:20::431; envelope-from=richard.henderson@linaro.org; helo=mail-pf1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/15/24 23:39, Chinmay Rath wrote: > The handler methods for divw[u] instructions internally use Rc(ctx->opcode), > for extraction of Rc field of instructions, which poses a problem if we move > the above said instructions to decodetree, as the ctx->opcode field is not > popluated in decodetree. Hence, making it decodetree compatible, so that the > mentioned insns can be safely move to decodetree specs. > > Signed-off-by: Chinmay Rath > --- > target/ppc/translate.c | 9 +++++---- > 1 file changed, 5 insertions(+), 4 deletions(-) Reviewed-by: Richard Henderson > +static inline void gen_op_arith_divw(DisasContext *ctx, TCGv ret, > + TCGv arg1, TCGv arg2, bool sign, > + bool compute_ov, bool compute_rc0) Could drop the inline at the same time. Let the compiler decide. r~