From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48795) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHcsb-0002FD-Ao for qemu-devel@nongnu.org; Mon, 27 Jun 2016 16:11:38 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bHcsW-0008Gx-9N for qemu-devel@nongnu.org; Mon, 27 Jun 2016 16:11:36 -0400 Received: from mail-qt0-x244.google.com ([2607:f8b0:400d:c0d::244]:32846) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bHcsW-0008Gs-4q for qemu-devel@nongnu.org; Mon, 27 Jun 2016 16:11:32 -0400 Received: by mail-qt0-x244.google.com with SMTP id f89so4200859qtd.0 for ; Mon, 27 Jun 2016 13:11:32 -0700 (PDT) Sender: Richard Henderson References: <1467054136-10430-1-git-send-email-cota@braap.org> <1467054136-10430-2-git-send-email-cota@braap.org> From: Richard Henderson Message-ID: Date: Mon, 27 Jun 2016 13:11:28 -0700 MIME-Version: 1.0 In-Reply-To: <1467054136-10430-2-git-send-email-cota@braap.org> Content-Type: text/plain; charset=windows-1252; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [RFC 01/30] softmmu: add cmpxchg helpers List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: "Emilio G. Cota" , QEMU Developers , MTTCG Devel Cc: Peter Maydell , Alvise Rigo , Sergey Fedorov , Paolo Bonzini , =?UTF-8?Q?Alex_Benn=c3=a9e?= On 06/27/2016 12:01 PM, Emilio G. Cota wrote: > Signed-off-by: Emilio G. Cota > --- > softmmu_template.h | 58 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ > tcg/tcg.h | 16 +++++++++++++++ > 2 files changed, 74 insertions(+) > > diff --git a/softmmu_template.h b/softmmu_template.h > index 208f808..7b519dc 100644 > --- a/softmmu_template.h > +++ b/softmmu_template.h > @@ -548,6 +548,64 @@ void probe_write(CPUArchState *env, target_ulong addr, int mmu_idx, > } > } > #endif > + > +DATA_TYPE > +glue(glue(helper_cmpxchg, SUFFIX), > + MMUSUFFIX)(CPUArchState *env, target_ulong addr, DATA_TYPE old, > + DATA_TYPE new, TCGMemOpIdx oi, uintptr_t retaddr) > +{ > + unsigned mmu_idx = get_mmuidx(oi); > + int index = (addr >> TARGET_PAGE_BITS) & (CPU_TLB_SIZE - 1); > + target_ulong tlb_addr = env->tlb_table[mmu_idx][index].addr_write; > + uintptr_t haddr; > + > + /* Adjust the given return address. */ > + retaddr -= GETPC_ADJ; > + > + /* If the TLB entry is for a different page, reload and try again. */ > + if ((addr & TARGET_PAGE_MASK) > + != (tlb_addr & (TARGET_PAGE_MASK | TLB_INVALID_MASK))) { > + if (unlikely((addr & (DATA_SIZE - 1)) != 0 > + && (get_memop(oi) & MO_AMASK) == MO_ALIGN)) { > + cpu_unaligned_access(ENV_GET_CPU(env), addr, MMU_DATA_STORE, > + mmu_idx, retaddr); > + } > + if (!VICTIM_TLB_HIT(addr_write)) { > + tlb_fill(ENV_GET_CPU(env), addr, MMU_DATA_STORE, mmu_idx, retaddr); > + } > + tlb_addr = env->tlb_table[mmu_idx][index].addr_write; > + } You need to verify that addr_read == addr_write as well, so that tlb_fill can signal an exception in the rare case of a guest attempting a cmpxchg on a write-only page. > + /* > + * If the host allows unaligned accesses, then let the compiler > + * do its thing when performing the access on the host. > + */ > + haddr = addr + env->tlb_table[mmu_idx][index].addend; > + return atomic_cmpxchg((DATA_TYPE *)haddr, old, new); Host endian operation? r~