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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a6d2236452sm8805107f8f.59.2025.06.23.02.30.37 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 23 Jun 2025 02:30:37 -0700 (PDT) Message-ID: Date: Mon, 23 Jun 2025 11:30:36 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 02/19] hw/pci: Introduce pci_device_get_viommu_cap() Content-Language: en-US To: "Duan, Zhenzhong" , "qemu-devel@nongnu.org" Cc: "alex.williamson@redhat.com" , "clg@redhat.com" , "mst@redhat.com" , "jasowang@redhat.com" , "peterx@redhat.com" , "ddutile@redhat.com" , "jgg@nvidia.com" , "nicolinc@nvidia.com" , "shameerali.kolothum.thodi@huawei.com" , "joao.m.martins@oracle.com" , "clement.mathieu--drif@eviden.com" , "Tian, Kevin" , "Liu, Yi L" , "Peng, Chao P" , Marcel Apfelbaum References: <20250620071813.55571-1-zhenzhong.duan@intel.com> <20250620071813.55571-3-zhenzhong.duan@intel.com> <15fa4c74-347f-4374-b225-d97f340d045b@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -30 X-Spam_score: -3.1 X-Spam_bar: --- X-Spam_report: (-3.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=-1, RCVD_IN_MSPIKE_WL=-0.01, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, RCVD_IN_VALIDITY_SAFE_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi Zhenzhong, On 6/23/25 4:20 AM, Duan, Zhenzhong wrote: > Hi Eric, > >> -----Original Message----- >> From: Eric Auger >> Subject: Re: [PATCH v2 02/19] hw/pci: Introduce pci_device_get_viommu_cap() >> >> Hi Zhenzhong, >> >> On 6/20/25 9:17 AM, Zhenzhong Duan wrote: >>> pci_device_get_viommu_cap() call pci_device_get_iommu_bus_devfn() >>> to get iommu_bus->iommu_ops and call get_viommu_cap() callback to >>> get a bitmap with each bit represents a vIOMMU exposed capability. >>> >>> Suggested-by: Yi Liu >>> Signed-off-by: Zhenzhong Duan >>> --- >>> include/hw/pci/pci.h | 22 ++++++++++++++++++++++ >>> hw/pci/pci.c | 11 +++++++++++ >>> 2 files changed, 33 insertions(+) >>> >>> diff --git a/include/hw/pci/pci.h b/include/hw/pci/pci.h >>> index df3cc7b875..829757b2c2 100644 >>> --- a/include/hw/pci/pci.h >>> +++ b/include/hw/pci/pci.h >>> @@ -453,6 +453,18 @@ typedef struct PCIIOMMUOps { >>> * @devfn: device and function number of the PCI device. >>> */ >>> void (*unset_iommu_device)(PCIBus *bus, void *opaque, int devfn); >>> + /** >>> + * @get_viommu_cap: get vIOMMU capabilities >>> + * >>> + * Optional callback, if not implemented, then vIOMMU doesn't >>> + * support exposing capabilities to other subsystem, e.g., VFIO. >>> + * vIOMMU can choose which capabilities to expose. >>> + * >>> + * @opaque: the data passed to pci_setup_iommu(). >>> + * >>> + * Returns: 64bit bitmap with each bit represents a capability. >> I think we need to clarify what this bitmap contains as capability bits >> (enum type) > Sure, will be like: > > * Returns: 64bit bitmap with each bit represents a capability emulated > * by VIOMMU_CAP_* in include/hw/iommu.h > > enum { > VIOMMU_CAP_STAGE1 = BIT_ULL(0), /* stage1 page table supported */ > }; looks good to me Eric > > Thanks > Zhenzhong >