From: Richard Henderson <richard.henderson@linaro.org>
To: Alistair Francis <alistair.francis@wdc.com>,
qemu-devel@nongnu.org, qemu-riscv@nongnu.org
Cc: alistair23@gmail.com, bmeng.cn@gmail.com, palmer@dabbelt.com
Subject: Re: [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode
Date: Fri, 23 Oct 2020 12:13:34 -0700 [thread overview]
Message-ID: <bec11f34-9cfe-4aa2-2f9c-3781d7f5e8ad@linaro.org> (raw)
In-Reply-To: <16213739a6232aa4824c5a008e2f669e6e58fbcf.1603466725.git.alistair.francis@wdc.com>
On 10/23/20 8:26 AM, Alistair Francis wrote:
> +++ b/target/riscv/cpu-param.h
> @@ -18,6 +18,6 @@
> # define TARGET_VIRT_ADDR_SPACE_BITS 32 /* sv32 */
> #endif
> #define TARGET_PAGE_BITS 12 /* 4 KiB Pages */
> -#define NB_MMU_MODES 4
> +#define NB_MMU_MODES 8
Is there really a PRV_M + virt enabled state?
> +#define TB_FLAGS_PRIV_MMU_MASK 3
...
> - int mode = mmu_idx;
> + int mode = mmu_idx & 0x3;
Use that MASK here?
r~
next prev parent reply other threads:[~2020-10-23 19:14 UTC|newest]
Thread overview: 8+ messages / expand[flat|nested] mbox.gz Atom feed top
2020-10-23 15:25 [PATCH v1 0/5] Fix the Hypervisor access functions Alistair Francis
2020-10-23 15:26 ` [PATCH v1 1/5] target/riscv: Add a virtualised MMU Mode Alistair Francis
2020-10-23 19:13 ` Richard Henderson [this message]
2020-10-23 23:29 ` Alistair Francis
2020-10-23 15:26 ` [PATCH v1 2/5] target/riscv: Set the virtualised MMU mode when doing hyp accesses Alistair Francis
2020-10-23 15:26 ` [PATCH v1 3/5] target/riscv: Remove the HS_TWO_STAGE flag Alistair Francis
2020-10-23 15:26 ` [PATCH v1 4/5] target/riscv: Remove the hyp load and store functions Alistair Francis
2020-10-23 15:26 ` [PATCH v1 5/5] target/riscv: Split the Hypervisor execute load helpers Alistair Francis
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