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Mon, 15 Apr 2024 02:41:14 -0700 (PDT) Message-ID: Date: Mon, 15 Apr 2024 11:41:12 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v4 4/5] hw/arm : Connect DM163 to B-L475E-IOT01A To: =?UTF-8?Q?In=C3=A8s_Varhol?= , qemu-devel@nongnu.org Cc: Paolo Bonzini , Thomas Huth , =?UTF-8?Q?Marc-Andr=C3=A9_Lureau?= , qemu-arm@nongnu.org, Laurent Vivier , Samuel Tardieu , Arnaud Minier , Peter Maydell References: <20240414130604.182059-1-ines.varhol@telecom-paris.fr> <20240414130604.182059-5-ines.varhol@telecom-paris.fr> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20240414130604.182059-5-ines.varhol@telecom-paris.fr> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::229; envelope-from=philmd@linaro.org; helo=mail-lj1-x229.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 14/4/24 15:05, Inès Varhol wrote: > Signed-off-by: Arnaud Minier > Signed-off-by: Inès Varhol > --- > hw/arm/b-l475e-iot01a.c | 59 +++++++++++++++++++++++++++++++++++++++-- > hw/arm/Kconfig | 1 + > 2 files changed, 58 insertions(+), 2 deletions(-) > +/* > + * There are actually 14 input pins in the DM163 device. > + * Here the DM163 input pin EN isn't connected to the STM32L4x5 > + * GPIOs as the IM120417002 colors shield doesn't actually use > + * this pin to drive the RGB matrix. > + */ > +#define NUM_DM163_INPUTS 13 > + > +static const int dm163_input[NUM_DM163_INPUTS] = { s/int/unsigned/ > + 1 * GPIO_NUM_PINS + 2, /* ROW0 PB2 */ > + 0 * GPIO_NUM_PINS + 15, /* ROW1 PA15 */ > + 0 * GPIO_NUM_PINS + 2, /* ROW2 PA2 */ > + 0 * GPIO_NUM_PINS + 7, /* ROW3 PA7 */ > + 0 * GPIO_NUM_PINS + 6, /* ROW4 PA6 */ > + 0 * GPIO_NUM_PINS + 5, /* ROW5 PA5 */ > + 1 * GPIO_NUM_PINS + 0, /* ROW6 PB0 */ > + 0 * GPIO_NUM_PINS + 3, /* ROW7 PA3 */ > + 0 * GPIO_NUM_PINS + 4, /* SIN (SDA) PA4 */ > + 1 * GPIO_NUM_PINS + 1, /* DCK (SCK) PB1 */ > + 2 * GPIO_NUM_PINS + 3, /* RST_B (RST) PC3 */ > + 2 * GPIO_NUM_PINS + 4, /* LAT_B (LAT) PC4 */ > + 2 * GPIO_NUM_PINS + 5, /* SELBK (SB) PC5 */ > +}; > > #define TYPE_B_L475E_IOT01A MACHINE_TYPE_NAME("b-l475e-iot01a") > OBJECT_DECLARE_SIMPLE_TYPE(Bl475eMachineState, B_L475E_IOT01A) > @@ -39,12 +66,16 @@ typedef struct Bl475eMachineState { > MachineState parent_obj; > > Stm32l4x5SocState soc; > + SplitIRQ gpio_splitters[NUM_DM163_INPUTS]; > + DM163State dm163; > } Bl475eMachineState; > > static void bl475e_init(MachineState *machine) > { > Bl475eMachineState *s = B_L475E_IOT01A(machine); > const Stm32l4x5SocClass *sc; > + DeviceState *dev, *gpio_out_splitter; > + int gpio, pin; unsigned. > > object_initialize_child(OBJECT(machine), "soc", &s->soc, > TYPE_STM32L4X5XG_SOC); > @@ -53,6 +84,30 @@ static void bl475e_init(MachineState *machine) > sc = STM32L4X5_SOC_GET_CLASS(&s->soc); > armv7m_load_kernel(ARM_CPU(first_cpu), > machine->kernel_filename, 0, sc->flash_size); > + > + if (object_class_by_name("dm163")) { TYPE_DM163 > + object_initialize_child(OBJECT(machine), "dm163", > + &s->dm163, TYPE_DM163); > + dev = DEVICE(&s->dm163); > + qdev_realize(dev, NULL, &error_abort); Reviewed-by: Philippe Mathieu-Daudé