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[176.184.10.225]) by smtp.gmail.com with ESMTPSA id a24-20020a50ff18000000b0050bc4eb9846sm12962042edu.1.2023.06.19.06.09.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 19 Jun 2023 06:10:09 -0700 (PDT) Message-ID: Date: Mon, 19 Jun 2023 15:09:44 +0200 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (Macintosh; Intel Mac OS X 10.15; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [PATCH v3] imx_serial: set wake bit when we receive a data byte Content-Language: en-US To: Peter Maydell , Martin Kaiser Cc: =?UTF-8?Q?Marc-Andr=c3=a9_Lureau?= , Paolo Bonzini , qemu-arm@nongnu.org, qemu-devel@nongnu.org References: <20230608154129.133169-1-martin@kaiser.cx> <20230615142256.1142849-1-martin@kaiser.cx> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= In-Reply-To: Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=2a00:1450:4864:20::52e; envelope-from=philmd@linaro.org; helo=mail-ed1-x52e.google.com X-Spam_score_int: -21 X-Spam_score: -2.2 X-Spam_bar: -- X-Spam_report: (-2.2 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, NICE_REPLY_A=-0.09, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 19/6/23 12:36, Peter Maydell wrote: > On Thu, 15 Jun 2023 at 15:24, Martin Kaiser wrote: >> >> The Linux kernel added a flood check for RX data recently in commit >> 496a4471b7c3 ("serial: imx: work-around for hardware RX flood"). This >> check uses the wake bit in the UART status register 2. The wake bit >> indicates that the receiver detected a start bit on the RX line. If the >> kernel sees a number of RX interrupts without the wake bit being set, it >> treats this as spurious data and resets the UART port. imx_serial does >> never set the wake bit and triggers the kernel's flood check. >> >> This patch adds support for the wake bit. wake is set when we receive a >> new character (it's not set for break events). It seems that wake is >> cleared by the kernel driver, the hardware does not have to clear it >> automatically after data was read. >> >> The wake bit can be configured as an interrupt source. Support this >> mechanism as well. >> >> Co-developed-by: Philippe Mathieu-Daudé Signed-off-by: Philippe Mathieu-Daudé >> Reviewed-by: Philippe Mathieu-Daudé >> Signed-off-by: Martin Kaiser > > > > Applied to target-arm.next, thanks. > > -- PMM