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From: Paolo Bonzini <pbonzini@redhat.com>
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Date: Wed, 5 Dec 2018 22:18:50 +0100
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Subject: Re: [Qemu-devel] Question about piix3's PIRQC register set
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To: Li Qiang <liq3ea@163.com>, Alex Williamson <alex.l.williamson@gmail.com>
Cc: "qemu-devel@nongnu.org" <qemu-devel@nongnu.org>

On 05/12/18 16:13, Li Qiang wrote:
> Here my question when the piix3=E2=80=99s PIRQx route control registers=
 is set
> and by who?
>=20
> I mean when this =E2=80=98=E2=80=98piix3->dev.config[PIIX_PIRQC + pin];=
=E2=80=99=E2=80=99 is set?
> =C2=A0
> Once I think this is set by seabios.

Hi,

it's set by the operating system via ACPI.  Search for define_link in
SeaBIOS's src/fw/acpi-dsdt.dsl, it refers to fields called PRQ0-PRQ3
which in turn are defined like this:

            /* PIIX PCI to ISA irq remapping */
            OperationRegion(P40C, PCI_Config, 0x60, 0x04)

	...
        Field(PCI0.ISA.P40C, ByteAcc, NoLock, Preserve) {
            PRQ0,   8,
            PRQ1,   8,
            PRQ2,   8,
            PRQ3,   8
        }

Current QEMU doesn't use anymore the SeaBIOS copy of the DSDT, but the
same thing can be found in build_piix4_isa_bridge and
build_piix4_pci0_int, in hw/i386/acpi-build.c.

> But seems it is not as this function is called in vfio_realize, the
> guest dones=E2=80=99t begin.

vfio also calls it (from vfio_intx_update) every time the routing
registers are updated.  The ISA bridge calls
pci_bus_fire_intx_routing_notifier, and then that function calls
vfio_intx_update, because it was registered with
pci_device_set_intx_routing_notifier.

Thanks,

Paolo