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[88.187.86.199]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3a53229d9adsm11335387f8f.9.2025.06.10.00.41.17 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 10 Jun 2025 00:41:17 -0700 (PDT) Message-ID: Date: Tue, 10 Jun 2025 09:41:16 +0200 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [PATCH v2 4/9] target/riscv: Add MIPS P8700 CSRs To: Djordje Todorovic , "qemu-devel@nongnu.org" Cc: "qemu-riscv@nongnu.org" , "cfu@mips.com" References: <20250602131226.1137281-1-djordje.todorovic@htecgroup.com> <20250602131226.1137281-5-djordje.todorovic@htecgroup.com> Content-Language: en-US From: =?UTF-8?Q?Philippe_Mathieu-Daud=C3=A9?= In-Reply-To: <20250602131226.1137281-5-djordje.todorovic@htecgroup.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=2a00:1450:4864:20::431; envelope-from=philmd@linaro.org; helo=mail-wr1-x431.google.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 2/6/25 15:12, Djordje Todorovic wrote: > Define MIPS CSRs used for P8700 CPU. > > Signed-off-by: Chao-ying Fu > Signed-off-by: Djordje Todorovic > --- > target/riscv/cpu.c | 3 + > target/riscv/cpu.h | 7 ++ > target/riscv/meson.build | 1 + > target/riscv/mips_csr.c | 219 +++++++++++++++++++++++++++++++++++++++ > 4 files changed, 230 insertions(+) > create mode 100644 target/riscv/mips_csr.c > diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h > index c0e048a66d..984f93dd4a 100644 > --- a/target/riscv/cpu.h > +++ b/target/riscv/cpu.h > @@ -497,6 +497,10 @@ struct CPUArchState { > target_ulong rnmip; > uint64_t rnmi_irqvec; > uint64_t rnmi_excpvec; > + > + uint64_t mipstvec; /* MIPS tvec register */ > + uint64_t mipsconfig[12]; /* MIPS config register */ > + uint64_t mipspmacfg[15]; /* MIPS pmacfg register */ Pointless comments (not helpful at all). Alternatively: struct { uint64_t tvec; uint64_t config[12]; uint64_t pmacfg[15]; } mips; > };