From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from lists.gnu.org (lists.gnu.org [209.51.188.17]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by smtp.lore.kernel.org (Postfix) with ESMTPS id 2B192C433F5 for ; Thu, 14 Apr 2022 02:19:14 +0000 (UTC) Received: from localhost ([::1]:51010 helo=lists1p.gnu.org) by lists.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nep4i-0000lQ-Uh for qemu-devel@archiver.kernel.org; Wed, 13 Apr 2022 22:19:12 -0400 Received: from eggs.gnu.org ([2001:470:142:3::10]:60472) by lists.gnu.org with esmtps (TLS1.2:ECDHE_RSA_AES_256_GCM_SHA384:256) (Exim 4.90_1) (envelope-from ) id 1nep3b-0007q7-Hz; Wed, 13 Apr 2022 22:18:03 -0400 Received: from smtp21.cstnet.cn ([159.226.251.21]:36176 helo=cstnet.cn) by eggs.gnu.org with esmtp (Exim 4.90_1) (envelope-from ) id 1nep3X-0007oL-Hs; Wed, 13 Apr 2022 22:18:03 -0400 Received: from [192.168.3.6] (unknown [180.156.147.178]) by APP-01 (Coremail) with SMTP id qwCowADHzd1HhFdiW8OoAQ--.16311S2; Thu, 14 Apr 2022 10:17:45 +0800 (CST) Subject: Re: [PATCH v9 12/14] target/riscv: rvk: add CSR support for Zkr To: Alistair Francis References: <20220318041944.19859-1-liweiwei@iscas.ac.cn> <20220318041944.19859-13-liweiwei@iscas.ac.cn> From: Weiwei Li Message-ID: Date: Thu, 14 Apr 2022 10:17:43 +0800 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:78.0) Gecko/20100101 Thunderbird/78.14.0 MIME-Version: 1.0 In-Reply-To: Content-Type: multipart/alternative; boundary="------------1FB461D85E0B53D6BE7EA579" Content-Language: en-US X-CM-TRANSID: qwCowADHzd1HhFdiW8OoAQ--.16311S2 X-Coremail-Antispam: 1UD129KBjvJXoW3Wr4ktw1rGrWruF4rJrWkWFg_yoWxKr1Upr 4UC3y5CrW8ZFZ7Cw4ftr15XF15Gr1rGa15Jws7W3yUAr43J3yrAFnYqwsIqFn8Xa1kGr42 9F4jkFnYkr47Za7anT9S1TB71UUUUUUqnTZGkaVYY2UrUUUUjbIjqfuFe4nvWSU5nxnvy2 9KBjDU0xBIdaVrnRJUUUmq14x267AKxVW8JVW5JwAFc2x0x2IEx4CE42xK8VAvwI8IcIk0 rVWrJVCq3wAFIxvE14AKwVWUJVWUGwA2ocxC64kIII0Yj41l84x0c7CEw4AK67xGY2AK02 1l84ACjcxK6xIIjxv20xvE14v26ryj6F1UM28EF7xvwVC0I7IYx2IY6xkF7I0E14v26r4U JVWxJr1l84ACjcxK6I8E87Iv67AKxVW8Jr0_Cr1UM28EF7xvwVC2z280aVCY1x0267AKxV WxJr0_GcWle2I262IYc4CY6c8Ij28IcVAaY2xG8wAv7VC0I7IYx2IY67AKxVWUJVWUGwAv 7VC2z280aVAFwI0_Jr0_Gr1lOx8S6xCaFVCjc4AY6r1j6r4UM4x0Y48IcVAKI48JM4x0x7 Aq67IIx4CEVc8vx2IErcIFxwACY4xI67k04243AVAKzVAKj4xxM4IIrI8v6xkF7I0E8cxa n2IY04v7Mx8GjcxK6IxK0xIIj40E5I8CrwCYjI0SjxkI62AI1cAE67vIY487MxkF7I0Ew4 C26cxK6c8Ij28IcwCF04k20xvY0x0EwIxGrwCFx2IqxVCFs4IE7xkEbVWUJVW8JwC20s02 6c02F40E14v26r106r1rMI8I3I0E7480Y4vE14v26r106r1rMI8E67AF67kF1VAFwI0_Jw 0_GFylIxkGc2Ij64vIr41lIxAIcVC0I7IYx2IY67AKxVWUJVWUCwCI42IY6xIIjxv20xvE c7CjxVAFwI0_Gr0_Cr1lIxAIcVCF04k26cxKx2IYs7xG6rW3Jr0E3s1lIxAIcVC2z280aV AFwI0_Jr0_Gr1lIxAIcVC2z280aVCY1x0267AKxVW8JVW8Jr1l6VACY4xI67k04243AbIY CTnIWIevJa73UjIFyTuYvjfUnR6zUUUUU X-Originating-IP: [180.156.147.178] X-CM-SenderInfo: 5olzvxxzhlqxpvfd2hldfou0/ Received-SPF: pass client-ip=159.226.251.21; envelope-from=liweiwei@iscas.ac.cn; helo=cstnet.cn X-Spam_score_int: -41 X-Spam_score: -4.2 X-Spam_bar: ---- X-Spam_report: (-4.2 / 5.0 requ) BAYES_00=-1.9, HTML_MESSAGE=0.001, NICE_REPLY_A=-0.001, RCVD_IN_DNSWL_MED=-2.3, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, SPF_HELO_PASS=-0.001, SPF_PASS=-0.001, T_SCC_BODY_TEXT_LINE=-0.01 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: =?UTF-8?B?V2VpIFd1ICjlkLTkvJ8p?= , "open list:RISC-V" , lustrew@foxmail.com, wangjunqiang , Bin Meng , Richard Henderson , "qemu-devel@nongnu.org Developers" , Palmer Dabbelt , luruibo2000@163.com, Alistair Francis Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" This is a multi-part message in MIME format. --------------1FB461D85E0B53D6BE7EA579 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 8bit Thanks for your comments. 在 2022/4/14 上午7:57, Alistair Francis 写道: > On Mon, Apr 11, 2022 at 2:46 PM Weiwei Li wrote: >> Hi, any comments on this patch or patchset? >> >> Currently, read-only instruction to access Seed CSR is checked as a >> special case in helper_csrr as suggested in >> >> https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00146.html. > Ah sorry, I didn't realise you had updated this. > >> (The new version for that patch is in >> https://lists.nongnu.org/archive/html/qemu-riscv/2022-03/msg00156.html) >> >> Regards, >> >> Weiwei Li >> >> 在 2022/3/18 下午12:19, Weiwei Li 写道: >>> - add SEED CSR which must be accessed with a read-write instruction: >>> A read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/CSRRCI >>> with uimm=0 will raise an illegal instruction exception. >>> - add USEED, SSEED fields for MSECCFG CSR >>> >>> Co-authored-by: Ruibo Lu >>> Co-authored-by: Zewen Ye >>> Signed-off-by: Weiwei Li >>> Signed-off-by: Junqiang Wang >>> --- >>> target/riscv/cpu_bits.h | 9 ++++++ >>> target/riscv/csr.c | 68 ++++++++++++++++++++++++++++++++++++++++ >>> target/riscv/op_helper.c | 9 ++++++ >>> target/riscv/pmp.h | 8 +++-- >>> 4 files changed, 91 insertions(+), 3 deletions(-) >>> >>> diff --git a/target/riscv/cpu_bits.h b/target/riscv/cpu_bits.h >>> index bb47cf7e77..d401100f47 100644 >>> --- a/target/riscv/cpu_bits.h >>> +++ b/target/riscv/cpu_bits.h >>> @@ -458,6 +458,9 @@ >>> #define CSR_VSPMMASK 0x2c1 >>> #define CSR_VSPMBASE 0x2c2 >>> >>> +/* Crypto Extension */ >>> +#define CSR_SEED 0x015 >>> + >>> /* mstatus CSR bits */ >>> #define MSTATUS_UIE 0x00000001 >>> #define MSTATUS_SIE 0x00000002 >>> @@ -800,4 +803,10 @@ typedef enum RISCVException { >>> #define HVICTL_VALID_MASK \ >>> (HVICTL_VTI | HVICTL_IID | HVICTL_IPRIOM | HVICTL_IPRIO) >>> >>> +/* seed CSR bits */ >>> +#define SEED_OPST (0b11 << 30) >>> +#define SEED_OPST_BIST (0b00 << 30) >>> +#define SEED_OPST_WAIT (0b01 << 30) >>> +#define SEED_OPST_ES16 (0b10 << 30) >>> +#define SEED_OPST_DEAD (0b11 << 30) >>> #endif >>> diff --git a/target/riscv/csr.c b/target/riscv/csr.c >>> index 3c61dd69af..5717a51f56 100644 >>> --- a/target/riscv/csr.c >>> +++ b/target/riscv/csr.c >>> @@ -24,6 +24,8 @@ >>> #include "qemu/main-loop.h" >>> #include "exec/exec-all.h" >>> #include "sysemu/cpu-timers.h" >>> +#include "qemu/guest-random.h" >>> +#include "qapi/error.h" >>> >>> /* CSR function table public API */ >>> void riscv_get_csr_ops(int csrno, riscv_csr_operations *ops) >>> @@ -292,6 +294,40 @@ static RISCVException epmp(CPURISCVState *env, int csrno) >>> } >>> #endif >>> >>> +static RISCVException seed(CPURISCVState *env, int csrno) >>> +{ >>> + RISCVCPU *cpu = env_archcpu(env); >>> + >>> + if (!cpu->cfg.ext_zkr) { >>> + return RISCV_EXCP_ILLEGAL_INST; >>> + } >>> + >>> +#if !defined(CONFIG_USER_ONLY) >>> + if (riscv_has_ext(env, RVS) && riscv_has_ext(env, RVH)) { >>> + /* Hypervisor extension is supported */ >>> + if (riscv_cpu_virt_enabled(env) && (env->priv != PRV_M)) { > You can simplify this to just riscv_cpu_virt_enabled(). You don't need > to check if we have the extension as well. Yeah, Maybe It can merge into following logic, like: if (env->priv == PRV_M) { //M return RISCV_EXCP_NONE; } else if (riscv_cpu_virt_enabled(env)) { //VS/VU if (env->mseccfg & MSECCFG_SSEED) { return RISCV_EXCP_NONE; } else { return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; } } else { //S/U if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { return RISCV_EXCP_NONE; } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { return RISCV_EXCP_NONE; } else { return RISCV_EXCP_ILLEGAL_INST; } } > >>> + if (env->mseccfg & MSECCFG_SSEED) { >>> + return RISCV_EXCP_VIRT_INSTRUCTION_FAULT; >>> + } else { >>> + return RISCV_EXCP_ILLEGAL_INST; >>> + } >>> + } >>> + } >>> + >>> + if (env->priv == PRV_M) { >>> + return RISCV_EXCP_NONE; >>> + } else if (env->priv == PRV_S && (env->mseccfg & MSECCFG_SSEED)) { >>> + return RISCV_EXCP_NONE; >>> + } else if (env->priv == PRV_U && (env->mseccfg & MSECCFG_USEED)) { >>> + return RISCV_EXCP_NONE; >>> + } else { >>> + return RISCV_EXCP_ILLEGAL_INST; >>> + } >>> +#else >>> + return RISCV_EXCP_NONE; >>> +#endif >>> +} >>> + >>> /* User Floating-Point CSRs */ >>> static RISCVException read_fflags(CPURISCVState *env, int csrno, >>> target_ulong *val) >>> @@ -2961,6 +2997,35 @@ static RISCVException write_upmbase(CPURISCVState *env, int csrno, >>> >>> #endif >>> >>> +/* Crypto Extension */ >>> +static RISCVException rmw_seed(CPURISCVState *env, int csrno, >>> + target_ulong *ret_value, >>> + target_ulong new_value, target_ulong write_mask) >>> +{ >>> + uint16_t random_v; >>> + Error *random_e = NULL; >>> + int random_r; >>> + >>> + random_r = qemu_guest_getrandom(&random_v, 2, &random_e); >>> + if (unlikely(random_r < 0)) { >>> + /* >>> + * Failed, for unknown reasons in the crypto subsystem. >>> + * The best we can do is log the reason and return a >>> + * failure indication to the guest. There is no reason >>> + * we know to expect the failure to be transitory, so >>> + * indicate DEAD to avoid having the guest spin on WAIT. >>> + */ >>> + qemu_log_mask(LOG_UNIMP, "%s: Crypto failure: %s", >>> + __func__, error_get_pretty(random_e)); >>> + error_free(random_e); >>> + *ret_value = SEED_OPST_DEAD; >>> + } else { >>> + *ret_value = random_v | SEED_OPST_ES16; >>> + } > Won't this seg fault if a guest does a CSR write? Yeah. Only CSR write seems have no function. However, it's not limited in the spec, so it's possible. I'll add NULL judgement here. > >>> + >>> + return RISCV_EXCP_NONE; >>> +} >>> + >>> /* >>> * riscv_csrrw - read and/or update control and status register >>> * >>> @@ -3205,6 +3270,9 @@ riscv_csr_operations csr_ops[CSR_TABLE_SIZE] = { >>> [CSR_TIME] = { "time", ctr, read_time }, >>> [CSR_TIMEH] = { "timeh", ctr32, read_timeh }, >>> >>> + /* Crypto Extension */ >>> + [CSR_SEED] = { "seed", seed, NULL, NULL, rmw_seed }, >>> + >>> #if !defined(CONFIG_USER_ONLY) >>> /* Machine Timers and Counters */ >>> [CSR_MCYCLE] = { "mcycle", any, read_instret }, >>> diff --git a/target/riscv/op_helper.c b/target/riscv/op_helper.c >>> index e0d708091e..3d8443416d 100644 >>> --- a/target/riscv/op_helper.c >>> +++ b/target/riscv/op_helper.c >>> @@ -39,6 +39,15 @@ void helper_raise_exception(CPURISCVState *env, uint32_t exception) >>> >>> target_ulong helper_csrr(CPURISCVState *env, int csr) >>> { >>> + /* >>> + * The seed CSR must be accessed with a read-write instruction. A >>> + * read-only instruction such as CSRRS/CSRRC with rs1=x0 or CSRRSI/ >>> + * CSRRCI with uimm=0 will raise an illegal instruction exception. >>> + */ >>> + if (csr == CSR_SEED) { >>> + riscv_raise_exception(env, RISCV_EXCP_ILLEGAL_INST, GETPC()); >>> + } >>> + >>> target_ulong val = 0; >>> RISCVException ret = riscv_csrrw(env, csr, &val, 0, 0, false); >>> >>> diff --git a/target/riscv/pmp.h b/target/riscv/pmp.h >>> index fcb6b7c467..a8dd797476 100644 >>> --- a/target/riscv/pmp.h >>> +++ b/target/riscv/pmp.h >>> @@ -39,9 +39,11 @@ typedef enum { >>> } pmp_am_t; >>> >>> typedef enum { >>> - MSECCFG_MML = 1 << 0, >>> - MSECCFG_MMWP = 1 << 1, >>> - MSECCFG_RLB = 1 << 2 >>> + MSECCFG_MML = 1 << 0, >>> + MSECCFG_MMWP = 1 << 1, >>> + MSECCFG_RLB = 1 << 2, > Why are these ones being changed? They are changed to align with MSECCFG_USEED. Is it OK or just let them unchanged? Regards, Weiwei Li > > Alistair > >>> + MSECCFG_USEED = 1 << 8, >>> + MSECCFG_SSEED = 1 << 9 >>> } mseccfg_field_t; >>> >>> typedef struct { >> --------------1FB461D85E0B53D6BE7EA579 Content-Type: text/html; charset=utf-8 Content-Transfer-Encoding: base64 PGh0bWw+CiAgPGhlYWQ+CiAgICA8bWV0YSBodHRwLWVxdWl2PSJDb250ZW50LVR5cGUiIGNv bnRlbnQ9InRleHQvaHRtbDsgY2hhcnNldD1VVEYtOCI+CiAgPC9oZWFkPgogIDxib2R5Pgog ICAgPHA+VGhhbmtzIGZvciB5b3VyIGNvbW1lbnRzLjxicj4KICAgIDwvcD4KICAgIDxkaXYg Y2xhc3M9Im1vei1jaXRlLXByZWZpeCI+5ZyoIDIwMjIvNC8xNCDkuIrljYg3OjU3LCBBbGlz dGFpciBGcmFuY2lzCiAgICAgIOWGmemBkzo8YnI+CiAgICA8L2Rpdj4KICAgIDxibG9ja3F1 b3RlIHR5cGU9ImNpdGUiCmNpdGU9Im1pZDpDQUttcXlLTytMekFPOVUxVHpodHJWbm1QRVRi amJTR3hkYlEtVD0zcEVxTHpUQVlpPUFAbWFpbC5nbWFpbC5jb20iPgogICAgICA8cHJlIGNs YXNzPSJtb3otcXVvdGUtcHJlIiB3cmFwPSIiPk9uIE1vbiwgQXByIDExLCAyMDIyIGF0IDI6 NDYgUE0gV2Vpd2VpIExpIDxhIGNsYXNzPSJtb3otdHh0LWxpbmstcmZjMjM5NkUiIGhyZWY9 Im1haWx0bzpsaXdlaXdlaUBpc2Nhcy5hYy5jbiI+Jmx0O2xpd2Vpd2VpQGlzY2FzLmFjLmNu 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