* [PULL 0/2] loongarch-to-apply queue
@ 2025-08-28 12:02 Song Gao
2025-08-28 12:02 ` [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro Song Gao
` (2 more replies)
0 siblings, 3 replies; 23+ messages in thread
From: Song Gao @ 2025-08-28 12:02 UTC (permalink / raw)
To: qemu-devel; +Cc: qemu-stable
The following changes since commit ca18b336e12c8433177a3cd639c5bf757952adaa:
Merge tag 'pull-lu-20250828' of https://gitlab.com/rth7680/qemu into staging (2025-08-28 09:24:36 +1000)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch-20250828
for you to fetch changes up to 86bca40402316891b8b9a920c2e3bf8cf37ba9a4:
hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue (2025-08-28 20:06:27 +0800)
----------------------------------------------------------------
pull-loongarch-20250828
----------------------------------------------------------------
Thomas Huth (1):
hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue
WANG Rui (1):
target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro
hw/intc/loongarch_pch_pic.c | 15 ++++-----
target/loongarch/tcg/insn_trans/trans_atomic.c.inc | 36 +++++++++++-----------
target/loongarch/tcg/insn_trans/trans_extra.c.inc | 8 +++--
target/loongarch/tcg/insn_trans/trans_farith.c.inc | 8 ++---
target/loongarch/tcg/insn_trans/trans_fcnv.c.inc | 4 +--
.../loongarch/tcg/insn_trans/trans_fmemory.c.inc | 16 +++++-----
.../tcg/insn_trans/trans_privileged.c.inc | 4 +--
target/loongarch/tcg/insn_trans/trans_shift.c.inc | 4 +--
target/loongarch/translate.h | 4 +++
9 files changed, 54 insertions(+), 45 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2025-08-28 12:02 [PULL 0/2] loongarch-to-apply queue Song Gao @ 2025-08-28 12:02 ` Song Gao 2025-09-11 10:04 ` Michael Tokarev 2025-08-28 12:02 ` [PULL 2/2] hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue Song Gao 2025-08-29 8:28 ` [PULL 0/2] loongarch-to-apply queue Richard Henderson 2 siblings, 1 reply; 23+ messages in thread From: Song Gao @ 2025-08-28 12:02 UTC (permalink / raw) To: qemu-devel; +Cc: qemu-stable, WANG Rui, Bibo Mao From: WANG Rui <wangrui@loongson.cn> This patch replaces uses of the generic TRANS macro with TRANS64 for instructions that are only valid when 64-bit support is available. This improves correctness and avoids potential assertion failures or undefined behavior during translation on 32-bit-only configurations. Signed-off-by: WANG Rui <wangrui@loongson.cn> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> --- .../tcg/insn_trans/trans_atomic.c.inc | 36 +++++++++---------- .../tcg/insn_trans/trans_extra.c.inc | 8 +++-- .../tcg/insn_trans/trans_farith.c.inc | 8 ++--- .../loongarch/tcg/insn_trans/trans_fcnv.c.inc | 4 +-- .../tcg/insn_trans/trans_fmemory.c.inc | 16 ++++----- .../tcg/insn_trans/trans_privileged.c.inc | 4 +-- .../tcg/insn_trans/trans_shift.c.inc | 4 +-- target/loongarch/translate.h | 4 +++ 8 files changed, 46 insertions(+), 38 deletions(-) diff --git a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc index 3d70d75941..77eeedbc42 100644 --- a/target/loongarch/tcg/insn_trans/trans_atomic.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_atomic.c.inc @@ -74,38 +74,38 @@ TRANS(sc_w, ALL, gen_sc, MO_TESL) TRANS(ll_d, 64, gen_ll, MO_TEUQ) TRANS(sc_d, 64, gen_sc, MO_TEUQ) TRANS(amswap_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) -TRANS(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) +TRANS64(amswap_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) TRANS(amadd_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) -TRANS(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) +TRANS64(amadd_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) TRANS(amand_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) -TRANS(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) +TRANS64(amand_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) TRANS(amor_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) -TRANS(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) +TRANS64(amor_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) TRANS(amxor_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) -TRANS(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) +TRANS64(amxor_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) TRANS(ammax_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) -TRANS(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) +TRANS64(ammax_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) TRANS(ammin_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) -TRANS(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) +TRANS64(ammin_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) TRANS(ammax_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) -TRANS(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) +TRANS64(ammax_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) TRANS(ammin_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) -TRANS(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) +TRANS64(ammin_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) TRANS(amswap_db_w, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TESL) -TRANS(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) +TRANS64(amswap_db_d, LAM, gen_am, tcg_gen_atomic_xchg_tl, MO_TEUQ) TRANS(amadd_db_w, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TESL) -TRANS(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) +TRANS64(amadd_db_d, LAM, gen_am, tcg_gen_atomic_fetch_add_tl, MO_TEUQ) TRANS(amand_db_w, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TESL) -TRANS(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) +TRANS64(amand_db_d, LAM, gen_am, tcg_gen_atomic_fetch_and_tl, MO_TEUQ) TRANS(amor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TESL) -TRANS(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) +TRANS64(amor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_or_tl, MO_TEUQ) TRANS(amxor_db_w, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TESL) -TRANS(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) +TRANS64(amxor_db_d, LAM, gen_am, tcg_gen_atomic_fetch_xor_tl, MO_TEUQ) TRANS(ammax_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TESL) -TRANS(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) +TRANS64(ammax_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smax_tl, MO_TEUQ) TRANS(ammin_db_w, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TESL) -TRANS(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) +TRANS64(ammin_db_d, LAM, gen_am, tcg_gen_atomic_fetch_smin_tl, MO_TEUQ) TRANS(ammax_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TESL) -TRANS(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) +TRANS64(ammax_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umax_tl, MO_TEUQ) TRANS(ammin_db_wu, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TESL) -TRANS(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) +TRANS64(ammin_db_du, LAM, gen_am, tcg_gen_atomic_fetch_umin_tl, MO_TEUQ) diff --git a/target/loongarch/tcg/insn_trans/trans_extra.c.inc b/target/loongarch/tcg/insn_trans/trans_extra.c.inc index eda3d6e561..298a80cff5 100644 --- a/target/loongarch/tcg/insn_trans/trans_extra.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_extra.c.inc @@ -69,6 +69,10 @@ static bool trans_rdtimeh_w(DisasContext *ctx, arg_rdtimeh_w *a) static bool trans_rdtime_d(DisasContext *ctx, arg_rdtime_d *a) { + if (!avail_64(ctx)) { + return false; + } + return gen_rdtime(ctx, a, 0, 0); } @@ -100,8 +104,8 @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a, TRANS(crc_w_b_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(1)) TRANS(crc_w_h_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(2)) TRANS(crc_w_w_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(4)) -TRANS(crc_w_d_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) +TRANS64(crc_w_d_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) TRANS(crcc_w_b_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(1)) TRANS(crcc_w_h_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(2)) TRANS(crcc_w_w_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(4)) -TRANS(crcc_w_d_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(8)) +TRANS64(crcc_w_d_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(8)) diff --git a/target/loongarch/tcg/insn_trans/trans_farith.c.inc b/target/loongarch/tcg/insn_trans/trans_farith.c.inc index f4a0dea727..ff6cf3448e 100644 --- a/target/loongarch/tcg/insn_trans/trans_farith.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_farith.c.inc @@ -183,16 +183,16 @@ TRANS(fmaxa_s, FP_SP, gen_fff, gen_helper_fmaxa_s) TRANS(fmaxa_d, FP_DP, gen_fff, gen_helper_fmaxa_d) TRANS(fmina_s, FP_SP, gen_fff, gen_helper_fmina_s) TRANS(fmina_d, FP_DP, gen_fff, gen_helper_fmina_d) -TRANS(fscaleb_s, FP_SP, gen_fff, gen_helper_fscaleb_s) -TRANS(fscaleb_d, FP_DP, gen_fff, gen_helper_fscaleb_d) +TRANS64(fscaleb_s, FP_SP, gen_fff, gen_helper_fscaleb_s) +TRANS64(fscaleb_d, FP_DP, gen_fff, gen_helper_fscaleb_d) TRANS(fsqrt_s, FP_SP, gen_ff, gen_helper_fsqrt_s) TRANS(fsqrt_d, FP_DP, gen_ff, gen_helper_fsqrt_d) TRANS(frecip_s, FP_SP, gen_ff, gen_helper_frecip_s) TRANS(frecip_d, FP_DP, gen_ff, gen_helper_frecip_d) TRANS(frsqrt_s, FP_SP, gen_ff, gen_helper_frsqrt_s) TRANS(frsqrt_d, FP_DP, gen_ff, gen_helper_frsqrt_d) -TRANS(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s) -TRANS(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d) +TRANS64(flogb_s, FP_SP, gen_ff, gen_helper_flogb_s) +TRANS64(flogb_d, FP_DP, gen_ff, gen_helper_flogb_d) TRANS(fclass_s, FP_SP, gen_ff, gen_helper_fclass_s) TRANS(fclass_d, FP_DP, gen_ff, gen_helper_fclass_d) TRANS(fmadd_s, FP_SP, gen_muladd, gen_helper_fmuladd_s, 0) diff --git a/target/loongarch/tcg/insn_trans/trans_fcnv.c.inc b/target/loongarch/tcg/insn_trans/trans_fcnv.c.inc index 833c059d6d..ca1d76a366 100644 --- a/target/loongarch/tcg/insn_trans/trans_fcnv.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_fcnv.c.inc @@ -29,5 +29,5 @@ TRANS(ffint_s_w, FP_SP, gen_ff, gen_helper_ffint_s_w) TRANS(ffint_s_l, FP_SP, gen_ff, gen_helper_ffint_s_l) TRANS(ffint_d_w, FP_DP, gen_ff, gen_helper_ffint_d_w) TRANS(ffint_d_l, FP_DP, gen_ff, gen_helper_ffint_d_l) -TRANS(frint_s, FP_SP, gen_ff, gen_helper_frint_s) -TRANS(frint_d, FP_DP, gen_ff, gen_helper_frint_d) +TRANS64(frint_s, FP_SP, gen_ff, gen_helper_frint_s) +TRANS64(frint_d, FP_DP, gen_ff, gen_helper_frint_d) diff --git a/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc b/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc index 13452bc7e5..79da4718a5 100644 --- a/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_fmemory.c.inc @@ -148,11 +148,11 @@ TRANS(fldx_s, FP_SP, gen_floadx, MO_TEUL) TRANS(fldx_d, FP_DP, gen_floadx, MO_TEUQ) TRANS(fstx_s, FP_SP, gen_fstorex, MO_TEUL) TRANS(fstx_d, FP_DP, gen_fstorex, MO_TEUQ) -TRANS(fldgt_s, FP_SP, gen_fload_gt, MO_TEUL) -TRANS(fldgt_d, FP_DP, gen_fload_gt, MO_TEUQ) -TRANS(fldle_s, FP_SP, gen_fload_le, MO_TEUL) -TRANS(fldle_d, FP_DP, gen_fload_le, MO_TEUQ) -TRANS(fstgt_s, FP_SP, gen_fstore_gt, MO_TEUL) -TRANS(fstgt_d, FP_DP, gen_fstore_gt, MO_TEUQ) -TRANS(fstle_s, FP_SP, gen_fstore_le, MO_TEUL) -TRANS(fstle_d, FP_DP, gen_fstore_le, MO_TEUQ) +TRANS64(fldgt_s, FP_SP, gen_fload_gt, MO_TEUL) +TRANS64(fldgt_d, FP_DP, gen_fload_gt, MO_TEUQ) +TRANS64(fldle_s, FP_SP, gen_fload_le, MO_TEUL) +TRANS64(fldle_d, FP_DP, gen_fload_le, MO_TEUQ) +TRANS64(fstgt_s, FP_SP, gen_fstore_gt, MO_TEUL) +TRANS64(fstgt_d, FP_DP, gen_fstore_gt, MO_TEUQ) +TRANS64(fstle_s, FP_SP, gen_fstore_le, MO_TEUL) +TRANS64(fstle_d, FP_DP, gen_fstore_le, MO_TEUQ) diff --git a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc index ecbfe23b63..34cfab8879 100644 --- a/target/loongarch/tcg/insn_trans/trans_privileged.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_privileged.c.inc @@ -233,11 +233,11 @@ static bool gen_iocsrwr(DisasContext *ctx, arg_rr *a, TRANS(iocsrrd_b, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_b) TRANS(iocsrrd_h, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_h) TRANS(iocsrrd_w, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_w) -TRANS(iocsrrd_d, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_d) +TRANS64(iocsrrd_d, IOCSR, gen_iocsrrd, gen_helper_iocsrrd_d) TRANS(iocsrwr_b, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_b) TRANS(iocsrwr_h, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_h) TRANS(iocsrwr_w, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_w) -TRANS(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d) +TRANS64(iocsrwr_d, IOCSR, gen_iocsrwr, gen_helper_iocsrwr_d) static void check_mmu_idx(DisasContext *ctx) { diff --git a/target/loongarch/tcg/insn_trans/trans_shift.c.inc b/target/loongarch/tcg/insn_trans/trans_shift.c.inc index 377307785a..136c4c8455 100644 --- a/target/loongarch/tcg/insn_trans/trans_shift.c.inc +++ b/target/loongarch/tcg/insn_trans/trans_shift.c.inc @@ -78,7 +78,7 @@ TRANS(sra_w, ALL, gen_rrr, EXT_SIGN, EXT_NONE, EXT_SIGN, gen_sra_w) TRANS(sll_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sll_d) TRANS(srl_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_srl_d) TRANS(sra_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_sra_d) -TRANS(rotr_w, 64, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w) +TRANS(rotr_w, ALL, gen_rrr, EXT_ZERO, EXT_NONE, EXT_SIGN, gen_rotr_w) TRANS(rotr_d, 64, gen_rrr, EXT_NONE, EXT_NONE, EXT_NONE, gen_rotr_d) TRANS(slli_w, ALL, gen_rri_c, EXT_NONE, EXT_SIGN, tcg_gen_shli_tl) TRANS(slli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shli_tl) @@ -86,5 +86,5 @@ TRANS(srli_w, ALL, gen_rri_c, EXT_ZERO, EXT_SIGN, tcg_gen_shri_tl) TRANS(srli_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_shri_tl) TRANS(srai_w, ALL, gen_rri_c, EXT_NONE, EXT_NONE, gen_sari_w) TRANS(srai_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_sari_tl) -TRANS(rotri_w, 64, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w) +TRANS(rotri_w, ALL, gen_rri_v, EXT_NONE, EXT_NONE, gen_rotr_w) TRANS(rotri_d, 64, gen_rri_c, EXT_NONE, EXT_NONE, tcg_gen_rotri_tl) diff --git a/target/loongarch/translate.h b/target/loongarch/translate.h index 018dc5eb17..bbe015ba57 100644 --- a/target/loongarch/translate.h +++ b/target/loongarch/translate.h @@ -14,6 +14,10 @@ static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ { return avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); } +#define TRANS64(NAME, AVAIL, FUNC, ...) \ + static bool trans_##NAME(DisasContext *ctx, arg_##NAME * a) \ + { return avail_64(ctx) && avail_##AVAIL(ctx) && FUNC(ctx, a, __VA_ARGS__); } + #define avail_ALL(C) true #define avail_64(C) (FIELD_EX32((C)->cpucfg1, CPUCFG1, ARCH) == \ CPUCFG1_ARCH_LA64) -- 2.47.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2025-08-28 12:02 ` [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro Song Gao @ 2025-09-11 10:04 ` Michael Tokarev 2025-09-11 10:30 ` Michael Tokarev 0 siblings, 1 reply; 23+ messages in thread From: Michael Tokarev @ 2025-09-11 10:04 UTC (permalink / raw) To: Song Gao, qemu-devel Cc: qemu-stable, WANG Rui, Bibo Mao, Clement Mathieu--Drif, Thomas Huth On 28.08.2025 15:02, Song Gao wrote: > From: WANG Rui <wangrui@loongson.cn> > > This patch replaces uses of the generic TRANS macro with TRANS64 for > instructions that are only valid when 64-bit support is available. > > This improves correctness and avoids potential assertion failures or > undefined behavior during translation on 32-bit-only configurations. Hi! This change has been CC'd to qemu-stable, apparently aimed for the previous qemu stable series as well. Current relevant long- term stable series is 10.0. However, this hunk: .. > --- a/target/loongarch/tcg/insn_trans/trans_extra.c.inc > +++ b/target/loongarch/tcg/insn_trans/trans_extra.c.inc > @@ -100,8 +104,8 @@ static bool gen_crc(DisasContext *ctx, arg_rrr *a, > TRANS(crc_w_b_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(1)) > TRANS(crc_w_h_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(2)) > TRANS(crc_w_w_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(4)) > -TRANS(crc_w_d_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) > +TRANS64(crc_w_d_w, CRC, gen_crc, gen_helper_crc32, tcg_constant_tl(8)) > TRANS(crcc_w_b_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(1)) > TRANS(crcc_w_h_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(2)) > TRANS(crcc_w_w_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(4)) > -TRANS(crcc_w_d_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(8)) > +TRANS64(crcc_w_d_w, CRC, gen_crc, gen_helper_crc32c, tcg_constant_tl(8)) does not apply to 10.0 directly, since 10.0 branch misses this: commit 256df51e727235b3d5e937ca2784c45663c00f59 Author: WANG Rui <wangrui@loongson.cn> Date: Fri Apr 18 16:21:01 2025 +0800 target/loongarch: Add CRC feature flag and use it to gate CRC instructions Since 10.0.x supposed to be a long-term series, are you okay if I pick commit 256df51e727235 to 10.0.x too, before this TRANS64 one? From the description of 256df51e727235 it looks like it should've been Cc'd qemu-stable too. What I'm thinking: for long-term stable series, it might be best to keep the code as close to the master branch as possible, and instead of adapting fixes from master to the context in the stable branch, it is often better to pick up preceeding changes and apply the fix as-is without modifications. The same applies to the second patch in this series, btw, -- the second patch also does not apply to 10.0.x directly because 10.0 lacks commit ab9bbee3c7da3 "hw/intc/loongarch_pch: Modify name of some registers" -- the commit is just some code renames, it does not change actual code, so it is a no-op, but it makes subsequent changes to not apply directly. I think I'll pick ab9bbee3c7da3 and the next one, 4f0f2ab5640ef "hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET..", to 10.0.x too. It looks like this code will receive more fixes in the future. And this' way, we can keep loongarch support in 10.0.x for longer and make it better. Does it all make sense? Thanks, /mjt ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2025-09-11 10:04 ` Michael Tokarev @ 2025-09-11 10:30 ` Michael Tokarev 2025-09-11 13:08 ` gaosong 0 siblings, 1 reply; 23+ messages in thread From: Michael Tokarev @ 2025-09-11 10:30 UTC (permalink / raw) To: Song Gao, qemu-devel Cc: qemu-stable, WANG Rui, Bibo Mao, Clement Mathieu--Drif, Thomas Huth On 11.09.2025 13:04, Michael Tokarev wrote: ... > The same applies to the second patch in this series, btw, -- the second > patch also does not apply to 10.0.x directly because 10.0 lacks commit > ab9bbee3c7da3 "hw/intc/loongarch_pch: Modify name of some registers" -- > the commit is just some code renames, it does not change actual code, so > it is a no-op, but it makes subsequent changes to not apply directly. > I think I'll pick ab9bbee3c7da3 and the next one, 4f0f2ab5640ef > "hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET..", > to 10.0.x too. And nope, the second patch ("loongarch_pch_pic: Fix ubsan warning and endianness issue") is a bit more involved in 10.0.x, since 10.0 also misses a6fdd0032ce5c7c "loongarch_pch: Use generic write callback for iomem8 region", which is one from larger refactoring series. Sigh. loongarch is a fast-moving target still.. :) Thanks, /mjt ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro 2025-09-11 10:30 ` Michael Tokarev @ 2025-09-11 13:08 ` gaosong 0 siblings, 0 replies; 23+ messages in thread From: gaosong @ 2025-09-11 13:08 UTC (permalink / raw) To: Michael Tokarev, qemu-devel Cc: qemu-stable, WANG Rui, Bibo Mao, Clement Mathieu--Drif, Thomas Huth 在 2025/9/11 下午6:30, Michael Tokarev 写道: > On 11.09.2025 13:04, Michael Tokarev wrote: > ... >> The same applies to the second patch in this series, btw, -- the second >> patch also does not apply to 10.0.x directly because 10.0 lacks commit >> ab9bbee3c7da3 "hw/intc/loongarch_pch: Modify name of some registers" -- >> the commit is just some code renames, it does not change actual code, so >> it is a no-op, but it makes subsequent changes to not apply directly. >> I think I'll pick ab9bbee3c7da3 and the next one, 4f0f2ab5640ef >> "hw/intc/loongarch_pch: Modify register name PCH_PIC_xxx_OFFSET..", >> to 10.0.x too. > > And nope, the second patch ("loongarch_pch_pic: Fix ubsan warning and > endianness issue") is a bit more involved in 10.0.x, since 10.0 also > misses a6fdd0032ce5c7c "loongarch_pch: Use generic write callback for > iomem8 region", which is one from larger refactoring series. Sigh. > hi, If these patches introduce too many dependencies, feel free to ignore them. This isn't a critical bug:-). Thanks. Song Gao > loongarch is a fast-moving target still.. :) > > Thanks, > > /mjt ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PULL 2/2] hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue 2025-08-28 12:02 [PULL 0/2] loongarch-to-apply queue Song Gao 2025-08-28 12:02 ` [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro Song Gao @ 2025-08-28 12:02 ` Song Gao 2025-08-29 8:28 ` [PULL 0/2] loongarch-to-apply queue Richard Henderson 2 siblings, 0 replies; 23+ messages in thread From: Song Gao @ 2025-08-28 12:02 UTC (permalink / raw) To: qemu-devel Cc: qemu-stable, Thomas Huth, Bibo Mao, Philippe Mathieu-Daudé From: Thomas Huth <thuth@redhat.com> When booting the Linux kernel from tests/functional/test_loongarch64_virt.py with a QEMU that has been compiled with --enable-ubsan, there is a warning like this: .../hw/intc/loongarch_pch_pic.c:171:46: runtime error: index 512 out of bounds for type 'uint8_t[64]' (aka 'unsigned char[64]') SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior .../hw/intc/loongarch_pch_pic.c:171:46 .../hw/intc/loongarch_pch_pic.c:175:45: runtime error: index 256 out of bounds for type 'uint8_t[64]' (aka 'unsigned char[64]') SUMMARY: UndefinedBehaviorSanitizer: undefined-behavior .../hw/intc/loongarch_pch_pic.c:175:45 It happens because "addr" is added first before substracting the base (PCH_PIC_HTMSI_VEC or PCH_PIC_ROUTE_ENTRY). Additionally, this code looks like it is not endianness safe, since it uses a 64-bit pointer to write values into an array of 8-bit values. Thus rework the code to use the stq_le_p / ldq_le_p helpers here and make sure that we do not create pointers with undefined behavior by accident. Signed-off-by: Thomas Huth <thuth@redhat.com> Reviewed-by: Bibo Mao <maobibo@loongson.cn> Reviewed-by: Philippe Mathieu-Daudé <philmd@linaro.org> Tested-by: Song Gao <gaosong@loongson.cn> Signed-off-by: Song Gao <gaosong@loongson.cn> --- hw/intc/loongarch_pch_pic.c | 15 ++++++++------- 1 file changed, 8 insertions(+), 7 deletions(-) diff --git a/hw/intc/loongarch_pch_pic.c b/hw/intc/loongarch_pch_pic.c index c4b242dbf4..32f01aabf0 100644 --- a/hw/intc/loongarch_pch_pic.c +++ b/hw/intc/loongarch_pch_pic.c @@ -110,10 +110,10 @@ static uint64_t pch_pic_read(void *opaque, hwaddr addr, uint64_t field_mask) val = s->int_polarity; break; case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: - val = *(uint64_t *)(s->htmsi_vector + addr - PCH_PIC_HTMSI_VEC); + val = ldq_le_p(&s->htmsi_vector[addr - PCH_PIC_HTMSI_VEC]); break; case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: - val = *(uint64_t *)(s->route_entry + addr - PCH_PIC_ROUTE_ENTRY); + val = ldq_le_p(&s->route_entry[addr - PCH_PIC_ROUTE_ENTRY]); break; default: qemu_log_mask(LOG_GUEST_ERROR, @@ -129,7 +129,8 @@ static void pch_pic_write(void *opaque, hwaddr addr, uint64_t value, { LoongArchPICCommonState *s = LOONGARCH_PIC_COMMON(opaque); uint32_t offset; - uint64_t old, mask, data, *ptemp; + uint64_t old, mask, data; + void *ptemp; offset = addr & 7; addr -= offset; @@ -168,12 +169,12 @@ static void pch_pic_write(void *opaque, hwaddr addr, uint64_t value, s->int_polarity = (s->int_polarity & ~mask) | data; break; case PCH_PIC_HTMSI_VEC ... PCH_PIC_HTMSI_VEC_END: - ptemp = (uint64_t *)(s->htmsi_vector + addr - PCH_PIC_HTMSI_VEC); - *ptemp = (*ptemp & ~mask) | data; + ptemp = &s->htmsi_vector[addr - PCH_PIC_HTMSI_VEC]; + stq_le_p(ptemp, (ldq_le_p(ptemp) & ~mask) | data); break; case PCH_PIC_ROUTE_ENTRY ... PCH_PIC_ROUTE_ENTRY_END: - ptemp = (uint64_t *)(s->route_entry + addr - PCH_PIC_ROUTE_ENTRY); - *ptemp = (*ptemp & ~mask) | data; + ptemp = (uint64_t *)&s->route_entry[addr - PCH_PIC_ROUTE_ENTRY]; + stq_le_p(ptemp, (ldq_le_p(ptemp) & ~mask) | data); break; default: qemu_log_mask(LOG_GUEST_ERROR, -- 2.47.0 ^ permalink raw reply related [flat|nested] 23+ messages in thread
* Re: [PULL 0/2] loongarch-to-apply queue 2025-08-28 12:02 [PULL 0/2] loongarch-to-apply queue Song Gao 2025-08-28 12:02 ` [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro Song Gao 2025-08-28 12:02 ` [PULL 2/2] hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue Song Gao @ 2025-08-29 8:28 ` Richard Henderson 2 siblings, 0 replies; 23+ messages in thread From: Richard Henderson @ 2025-08-29 8:28 UTC (permalink / raw) To: qemu-devel On 8/28/25 22:02, Song Gao wrote: > The following changes since commit ca18b336e12c8433177a3cd639c5bf757952adaa: > > Merge tag 'pull-lu-20250828' of https://gitlab.com/rth7680/qemu into staging (2025-08-28 09:24:36 +1000) > > are available in the Git repository at: > > https://github.com/gaosong715/qemu.git tags/pull-loongarch-20250828 > > for you to fetch changes up to 86bca40402316891b8b9a920c2e3bf8cf37ba9a4: > > hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue (2025-08-28 20:06:27 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20250828 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/10.2 as appropriate. r~ ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PULL 0/2] loongarch-to-apply queue
@ 2025-07-31 8:53 Song Gao
2025-08-01 19:34 ` Stefan Hajnoczi
0 siblings, 1 reply; 23+ messages in thread
From: Song Gao @ 2025-07-31 8:53 UTC (permalink / raw)
To: qemu-devel; +Cc: stefanha, qemu-stable
The following changes since commit 4e06566dbd1b1251c2788af26a30bd148d4eb6c1:
Merge tag 'pull-riscv-to-apply-20250730-2' of https://github.com/alistair23/qemu into staging (2025-07-30 09:59:30 -0400)
are available in the Git repository at:
https://github.com/gaosong715/qemu.git tags/pull-loongarch-20250731
for you to fetch changes up to 31995cc4087123a13e9345153e0c39ffb44b9277:
hw/intc/loongarch_ipi: Fix start fail with smp cpu < smp maxcpus on KVM (2025-07-31 16:57:01 +0800)
----------------------------------------------------------------
pull-loongarch-2025-0731-for-10.1
----------------------------------------------------------------
Bibo Mao (1):
target/loongarch: Fix valid virtual address checking
Song Gao (1):
hw/intc/loongarch_ipi: Fix start fail with smp cpu < smp maxcpus on KVM
hw/intc/loongarch_ipi_kvm.c | 27 ++++++++++++++++-----------
target/loongarch/cpu_helper.c | 4 ++--
2 files changed, 18 insertions(+), 13 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PULL 0/2] loongarch-to-apply queue 2025-07-31 8:53 Song Gao @ 2025-08-01 19:34 ` Stefan Hajnoczi 0 siblings, 0 replies; 23+ messages in thread From: Stefan Hajnoczi @ 2025-08-01 19:34 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel, stefanha, qemu-stable [-- Attachment #1: Type: text/plain, Size: 116 bytes --] Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/10.1 for any user-visible changes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PULL 0/2] loongarch-to-apply queue
@ 2024-01-25 7:15 Song Gao
2024-01-26 13:09 ` Peter Maydell
0 siblings, 1 reply; 23+ messages in thread
From: Song Gao @ 2024-01-25 7:15 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell
The following changes since commit 4a4efae44f19528589204581e9e2fab69c5d39aa:
Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging (2024-01-23 13:40:45 +0000)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240125
for you to fetch changes up to fc70099621fe7002d30fc1509456d1ae57264aa6:
target/loongarch/kvm: Enable LSX/LASX extension (2024-01-25 15:25:31 +0800)
----------------------------------------------------------------
pull-loongarch-20240125
----------------------------------------------------------------
Bibo Mao (1):
target/loongarch: Set cpuid CSR register only once with kvm mode
Song Gao (1):
target/loongarch/kvm: Enable LSX/LASX extension
linux-headers/asm-loongarch/kvm.h | 1 +
target/loongarch/kvm/kvm.c | 54 +++++++++++++++++++++++++++++++--------
2 files changed, 45 insertions(+), 10 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PULL 0/2] loongarch-to-apply queue 2024-01-25 7:15 Song Gao @ 2024-01-26 13:09 ` Peter Maydell 0 siblings, 0 replies; 23+ messages in thread From: Peter Maydell @ 2024-01-26 13:09 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel On Thu, 25 Jan 2024 at 07:31, Song Gao <gaosong@loongson.cn> wrote: > > The following changes since commit 4a4efae44f19528589204581e9e2fab69c5d39aa: > > Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging (2024-01-23 13:40:45 +0000) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240125 > > for you to fetch changes up to fc70099621fe7002d30fc1509456d1ae57264aa6: > > target/loongarch/kvm: Enable LSX/LASX extension (2024-01-25 15:25:31 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20240125 > > ---------------------------------------------------------------- Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PULL 0/2] loongarch-to-apply queue
@ 2024-01-25 7:15 Song Gao
0 siblings, 0 replies; 23+ messages in thread
From: Song Gao @ 2024-01-25 7:15 UTC (permalink / raw)
Cc: qemu-devel, peter.maydell
The following changes since commit 4a4efae44f19528589204581e9e2fab69c5d39aa:
Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging (2024-01-23 13:40:45 +0000)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240125
for you to fetch changes up to fc70099621fe7002d30fc1509456d1ae57264aa6:
target/loongarch/kvm: Enable LSX/LASX extension (2024-01-25 15:25:31 +0800)
----------------------------------------------------------------
pull-loongarch-20240125
----------------------------------------------------------------
Bibo Mao (1):
target/loongarch: Set cpuid CSR register only once with kvm mode
Song Gao (1):
target/loongarch/kvm: Enable LSX/LASX extension
linux-headers/asm-loongarch/kvm.h | 1 +
target/loongarch/kvm/kvm.c | 54 +++++++++++++++++++++++++++++++--------
2 files changed, 45 insertions(+), 10 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* [PULL 0/2] loongarch-to-apply queue
@ 2024-01-25 7:13 Song Gao
0 siblings, 0 replies; 23+ messages in thread
From: Song Gao @ 2024-01-25 7:13 UTC (permalink / raw)
Cc: qemu-devel, peter.maydell
The following changes since commit 4a4efae44f19528589204581e9e2fab69c5d39aa:
Merge tag 'pull-hex-20240121' of https://github.com/quic/qemu into staging (2024-01-23 13:40:45 +0000)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240125
for you to fetch changes up to fc70099621fe7002d30fc1509456d1ae57264aa6:
target/loongarch/kvm: Enable LSX/LASX extension (2024-01-25 15:25:31 +0800)
----------------------------------------------------------------
pull-loongarch-20240125
----------------------------------------------------------------
Bibo Mao (1):
target/loongarch: Set cpuid CSR register only once with kvm mode
Song Gao (1):
target/loongarch/kvm: Enable LSX/LASX extension
linux-headers/asm-loongarch/kvm.h | 1 +
target/loongarch/kvm/kvm.c | 54 +++++++++++++++++++++++++++++++--------
2 files changed, 45 insertions(+), 10 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* [PULL 0/2] loongarch-to-apply queue
@ 2024-01-05 1:17 Song Gao
2024-01-05 13:34 ` Peter Maydell
0 siblings, 1 reply; 23+ messages in thread
From: Song Gao @ 2024-01-05 1:17 UTC (permalink / raw)
To: peter.maydell; +Cc: qemu-devel
The following changes since commit d328fef93ae757a0dd65ed786a4086e27952eef3:
Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging (2024-01-04 10:23:34 +0000)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240105
for you to fetch changes up to 0cd8b379081fa71c23836052feb65da4685f8ec7:
target/loongarch: move translate modules to tcg/ (2024-01-05 09:31:05 +0800)
----------------------------------------------------------------
pull-loongarch-20240105
----------------------------------------------------------------
Song Gao (2):
target/loongarch/meson: move gdbstub.c to loongarch.ss
target/loongarch: move translate modules to tcg/
target/loongarch/meson.build | 15 +--------------
target/loongarch/{ => tcg}/constant_timer.c | 0
target/loongarch/{ => tcg}/csr_helper.c | 0
target/loongarch/{ => tcg}/fpu_helper.c | 0
.../loongarch/{ => tcg}/insn_trans/trans_arith.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_atomic.c.inc | 0
target/loongarch/{ => tcg}/insn_trans/trans_bit.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_branch.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_extra.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_farith.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_fcmp.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_fcnv.c.inc | 0
.../{ => tcg}/insn_trans/trans_fmemory.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_fmov.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_memory.c.inc | 0
.../{ => tcg}/insn_trans/trans_privileged.c.inc | 0
.../loongarch/{ => tcg}/insn_trans/trans_shift.c.inc | 0
target/loongarch/{ => tcg}/insn_trans/trans_vec.c.inc | 0
target/loongarch/{ => tcg}/iocsr_helper.c | 0
target/loongarch/tcg/meson.build | 19 +++++++++++++++++++
target/loongarch/{ => tcg}/op_helper.c | 0
target/loongarch/{ => tcg}/tlb_helper.c | 0
target/loongarch/{ => tcg}/translate.c | 0
target/loongarch/{ => tcg}/vec_helper.c | 0
24 files changed, 20 insertions(+), 14 deletions(-)
rename target/loongarch/{ => tcg}/constant_timer.c (100%)
rename target/loongarch/{ => tcg}/csr_helper.c (100%)
rename target/loongarch/{ => tcg}/fpu_helper.c (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_arith.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_atomic.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_bit.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_branch.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_extra.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_farith.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fcmp.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fcnv.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fmemory.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_fmov.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_memory.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_privileged.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_shift.c.inc (100%)
rename target/loongarch/{ => tcg}/insn_trans/trans_vec.c.inc (100%)
rename target/loongarch/{ => tcg}/iocsr_helper.c (100%)
create mode 100644 target/loongarch/tcg/meson.build
rename target/loongarch/{ => tcg}/op_helper.c (100%)
rename target/loongarch/{ => tcg}/tlb_helper.c (100%)
rename target/loongarch/{ => tcg}/translate.c (100%)
rename target/loongarch/{ => tcg}/vec_helper.c (100%)
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PULL 0/2] loongarch-to-apply queue 2024-01-05 1:17 Song Gao @ 2024-01-05 13:34 ` Peter Maydell 2024-01-06 1:18 ` gaosong 0 siblings, 1 reply; 23+ messages in thread From: Peter Maydell @ 2024-01-05 13:34 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel On Fri, 5 Jan 2024 at 01:30, Song Gao <gaosong@loongson.cn> wrote: > > The following changes since commit d328fef93ae757a0dd65ed786a4086e27952eef3: > > Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging (2024-01-04 10:23:34 +0000) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240105 > > for you to fetch changes up to 0cd8b379081fa71c23836052feb65da4685f8ec7: > > target/loongarch: move translate modules to tcg/ (2024-01-05 09:31:05 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20240105 > > ---------------------------------------------------------------- > Song Gao (2): > target/loongarch/meson: move gdbstub.c to loongarch.ss > target/loongarch: move translate modules to tcg/ Hi; this fails to build, with ../target/loongarch/tcg/meson.build:1:3: ERROR: Unknown variable "config_all". (eg https://gitlab.com/qemu-project/qemu/-/jobs/5868662017) I think your pullreq has unfortunately got a conflict with the meson cleanup patches that I just applied from Paolo. Could you have a look at this and respin the pullreq, please? thanks -- PMM ^ permalink raw reply [flat|nested] 23+ messages in thread
* Re: [PULL 0/2] loongarch-to-apply queue 2024-01-05 13:34 ` Peter Maydell @ 2024-01-06 1:18 ` gaosong 0 siblings, 0 replies; 23+ messages in thread From: gaosong @ 2024-01-06 1:18 UTC (permalink / raw) To: Peter Maydell; +Cc: qemu-devel 在 2024/1/5 下午9:34, Peter Maydell 写道: > On Fri, 5 Jan 2024 at 01:30, Song Gao <gaosong@loongson.cn> wrote: >> The following changes since commit d328fef93ae757a0dd65ed786a4086e27952eef3: >> >> Merge tag 'pull-20231230' of https://gitlab.com/rth7680/qemu into staging (2024-01-04 10:23:34 +0000) >> >> are available in the Git repository at: >> >> https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20240105 >> >> for you to fetch changes up to 0cd8b379081fa71c23836052feb65da4685f8ec7: >> >> target/loongarch: move translate modules to tcg/ (2024-01-05 09:31:05 +0800) >> >> ---------------------------------------------------------------- >> pull-loongarch-20240105 >> >> ---------------------------------------------------------------- >> Song Gao (2): >> target/loongarch/meson: move gdbstub.c to loongarch.ss >> target/loongarch: move translate modules to tcg/ > Hi; this fails to build, with > > ../target/loongarch/tcg/meson.build:1:3: ERROR: Unknown variable "config_all". > > (eg https://gitlab.com/qemu-project/qemu/-/jobs/5868662017) > > I think your pullreq has unfortunately got a conflict with the > meson cleanup patches that I just applied from Paolo. > > Could you have a look at this and respin the pullreq, please? Sure, I will. Thanks. Song Gao. ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PULL 0/2] loongarch-to-apply queue
@ 2023-12-21 8:06 Song Gao
2023-12-22 16:17 ` Stefan Hajnoczi
0 siblings, 1 reply; 23+ messages in thread
From: Song Gao @ 2023-12-21 8:06 UTC (permalink / raw)
To: qemu-devel; +Cc: stefanha, peter.maydell, richard.henderson
The following changes since commit 191710c221f65b1542f6ea7fa4d30dde6e134fd7:
Merge tag 'pull-request-2023-12-20' of https://gitlab.com/thuth/qemu into staging (2023-12-20 09:40:16 -0500)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20231221
for you to fetch changes up to be45144bee708d3b84c3c474a4d4aeb7e5c4733a:
target/loongarch: Add timer information dump support (2023-12-21 16:07:47 +0800)
----------------------------------------------------------------
pull-loongarch-20231221
----------------------------------------------------------------
Bibo Mao (2):
hw/loongarch/virt: Align high memory base address with super page size
target/loongarch: Add timer information dump support
include/hw/loongarch/virt.h | 2 +-
target/loongarch/cpu.c | 2 ++
2 files changed, 3 insertions(+), 1 deletion(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PULL 0/2] loongarch-to-apply queue 2023-12-21 8:06 Song Gao @ 2023-12-22 16:17 ` Stefan Hajnoczi 0 siblings, 0 replies; 23+ messages in thread From: Stefan Hajnoczi @ 2023-12-22 16:17 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel, stefanha, peter.maydell, richard.henderson [-- Attachment #1: Type: text/plain, Size: 115 bytes --] Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/9.0 for any user-visible changes. [-- Attachment #2: signature.asc --] [-- Type: application/pgp-signature, Size: 488 bytes --] ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PULL 0/2] loongarch-to-apply queue
@ 2023-10-08 7:03 Song Gao
0 siblings, 0 replies; 23+ messages in thread
From: Song Gao @ 2023-10-08 7:03 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson
The following changes since commit 2f3913f4b2ad74baeb5a6f1d36efbd9ecdf1057d:
Merge tag 'for_upstream' of https://git.kernel.org/pub/scm/virt/kvm/mst/qemu into staging (2023-10-05 09:01:01 -0400)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20231008
for you to fetch changes up to e1fc0cf1fb65c5f049bef4661d0e3278e51e2560:
target/loongarch: Add preldx instruction (2023-10-08 15:02:15 +0800)
----------------------------------------------------------------
pull-loongarch-20231008
----------------------------------------------------------------
Jiajie Chen (1):
target/loongarch: fix ASXE flag conflict
Song Gao (1):
target/loongarch: Add preldx instruction
target/loongarch/cpu.h | 4 ++--
target/loongarch/disas.c | 7 +++++++
target/loongarch/insn_trans/trans_memory.c.inc | 5 +++++
target/loongarch/insns.decode | 3 +++
4 files changed, 17 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* [PULL 0/2] loongarch-to-apply queue
@ 2023-05-26 9:27 Song Gao
2023-05-26 16:17 ` Richard Henderson
0 siblings, 1 reply; 23+ messages in thread
From: Song Gao @ 2023-05-26 9:27 UTC (permalink / raw)
To: qemu-devel; +Cc: richard.henderson
The following changes since commit a3cb6d5004ff638aefe686ecd540718a793bd1b1:
Merge tag 'pull-tcg-20230525' of https://gitlab.com/rth7680/qemu into staging (2023-05-25 11:11:52 -0700)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230526
for you to fetch changes up to 65bfaaae6ac79ebc623acc0ce28cc3bd4fe8b5e5:
target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump (2023-05-26 17:21:16 +0800)
----------------------------------------------------------------
pull-loongarch-20230526
----------------------------------------------------------------
Song Gao (2):
target/loongarch: Fix LD/ST{LE/GT} instructions get wrong CSR_ERA and CSR_BADV
target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump
target/loongarch/cpu.c | 2 +-
target/loongarch/insn_trans/trans_lsx.c.inc | 39 +++++++++++++++++++----------
target/loongarch/op_helper.c | 6 +++--
3 files changed, 31 insertions(+), 16 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PULL 0/2] loongarch-to-apply queue 2023-05-26 9:27 Song Gao @ 2023-05-26 16:17 ` Richard Henderson 0 siblings, 0 replies; 23+ messages in thread From: Richard Henderson @ 2023-05-26 16:17 UTC (permalink / raw) To: Song Gao, qemu-devel On 5/26/23 02:27, Song Gao wrote: > The following changes since commit a3cb6d5004ff638aefe686ecd540718a793bd1b1: > > Merge tag 'pull-tcg-20230525' ofhttps://gitlab.com/rth7680/qemu into staging (2023-05-25 11:11:52 -0700) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230526 > > for you to fetch changes up to 65bfaaae6ac79ebc623acc0ce28cc3bd4fe8b5e5: > > target/loongarch: Fix the vinsgr2vr/vpickve2gr instructions cause system coredump (2023-05-26 17:21:16 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20230526 Applied, thanks. Please update https://wiki.qemu.org/ChangeLog/8.1 as appropriate. r~ ^ permalink raw reply [flat|nested] 23+ messages in thread
* [PULL 0/2] loongarch-to-apply queue
@ 2023-04-04 11:38 Song Gao
2023-04-04 16:01 ` Peter Maydell
0 siblings, 1 reply; 23+ messages in thread
From: Song Gao @ 2023-04-04 11:38 UTC (permalink / raw)
To: qemu-devel; +Cc: peter.maydell, richard.henderson
The following changes since commit efcd0ec14b0fe9ee0ee70277763b2d538d19238d:
Merge tag 'misc-fixes-20230330' of https://github.com/philmd/qemu into staging (2023-03-30 14:22:29 +0100)
are available in the Git repository at:
https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230404
for you to fetch changes up to ec28dd6c6fc1366504003c25828953cac49e2da7:
target/loongarch: Enables plugins to get instruction codes (2023-04-04 19:33:23 +0800)
----------------------------------------------------------------
pull-loongarch-20230404
----------------------------------------------------------------
Tianrui Zhao (1):
hw/loongarch/virt: Fix virt_to_phys_addr function
tanhongze (1):
target/loongarch: Enables plugins to get instruction codes
hw/loongarch/virt.c | 2 +-
target/loongarch/translate.c | 2 +-
2 files changed, 2 insertions(+), 2 deletions(-)
^ permalink raw reply [flat|nested] 23+ messages in thread* Re: [PULL 0/2] loongarch-to-apply queue 2023-04-04 11:38 Song Gao @ 2023-04-04 16:01 ` Peter Maydell 0 siblings, 0 replies; 23+ messages in thread From: Peter Maydell @ 2023-04-04 16:01 UTC (permalink / raw) To: Song Gao; +Cc: qemu-devel, richard.henderson On Tue, 4 Apr 2023 at 12:38, Song Gao <gaosong@loongson.cn> wrote: > > The following changes since commit efcd0ec14b0fe9ee0ee70277763b2d538d19238d: > > Merge tag 'misc-fixes-20230330' of https://github.com/philmd/qemu into staging (2023-03-30 14:22:29 +0100) > > are available in the Git repository at: > > https://gitlab.com/gaosong/qemu.git tags/pull-loongarch-20230404 > > for you to fetch changes up to ec28dd6c6fc1366504003c25828953cac49e2da7: > > target/loongarch: Enables plugins to get instruction codes (2023-04-04 19:33:23 +0800) > > ---------------------------------------------------------------- > pull-loongarch-20230404 > Applied, thanks. Please update the changelog at https://wiki.qemu.org/ChangeLog/8.0 for any user-visible changes. -- PMM ^ permalink raw reply [flat|nested] 23+ messages in thread
end of thread, other threads:[~2025-09-11 13:10 UTC | newest] Thread overview: 23+ messages (download: mbox.gz follow: Atom feed -- links below jump to the message on this page -- 2025-08-28 12:02 [PULL 0/2] loongarch-to-apply queue Song Gao 2025-08-28 12:02 ` [PULL 1/2] target/loongarch: Guard 64-bit-only insn translation with TRANS64 macro Song Gao 2025-09-11 10:04 ` Michael Tokarev 2025-09-11 10:30 ` Michael Tokarev 2025-09-11 13:08 ` gaosong 2025-08-28 12:02 ` [PULL 2/2] hw/intc/loongarch_pch_pic: Fix ubsan warning and endianness issue Song Gao 2025-08-29 8:28 ` [PULL 0/2] loongarch-to-apply queue Richard Henderson -- strict thread matches above, loose matches on Subject: below -- 2025-07-31 8:53 Song Gao 2025-08-01 19:34 ` Stefan Hajnoczi 2024-01-25 7:15 Song Gao 2024-01-26 13:09 ` Peter Maydell 2024-01-25 7:15 Song Gao 2024-01-25 7:13 Song Gao 2024-01-05 1:17 Song Gao 2024-01-05 13:34 ` Peter Maydell 2024-01-06 1:18 ` gaosong 2023-12-21 8:06 Song Gao 2023-12-22 16:17 ` Stefan Hajnoczi 2023-10-08 7:03 Song Gao 2023-05-26 9:27 Song Gao 2023-05-26 16:17 ` Richard Henderson 2023-04-04 11:38 Song Gao 2023-04-04 16:01 ` Peter Maydell
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