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[88.21.202.78]) by smtp.gmail.com with ESMTPSA id g25sm4621021wmh.3.2020.02.18.09.23.47 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 18 Feb 2020 09:23:47 -0800 (PST) Subject: Re: [PATCH v5 34/79] arm/xilinx_zynq: drop RAM size fixup To: Igor Mammedov , qemu-devel@nongnu.org References: <20200217173452.15243-1-imammedo@redhat.com> <20200217173452.15243-35-imammedo@redhat.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Message-ID: Date: Tue, 18 Feb 2020 18:23:47 +0100 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:68.0) Gecko/20100101 Thunderbird/68.4.1 MIME-Version: 1.0 In-Reply-To: <20200217173452.15243-35-imammedo@redhat.com> Content-Language: en-US X-MC-Unique: iRIN22lTPGugjElLKwc5SQ-1 X-Mimecast-Spam-Score: 0 X-Mimecast-Originator: redhat.com Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] [fuzzy] X-Received-From: 207.211.31.120 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: Paolo Bonzini Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 2/17/20 6:34 PM, Igor Mammedov wrote: > If user provided non-sense RAM size, board will complain and > continue running with max RAM size supported. > Also RAM is going to be allocated by generic code, so it won't be > possible for board to fix things up for user. > > Make it error message and exit to force user fix CLI, > instead of accepting non-sense CLI values. > > Signed-off-by: Igor Mammedov > Reviewed-by: Alistair Francis > --- > hw/arm/xilinx_zynq.c | 16 ++++++++-------- > 1 file changed, 8 insertions(+), 8 deletions(-) > > diff --git a/hw/arm/xilinx_zynq.c b/hw/arm/xilinx_zynq.c > index 3a0fa5b23f..df950fc400 100644 > --- a/hw/arm/xilinx_zynq.c > +++ b/hw/arm/xilinx_zynq.c > @@ -158,7 +158,6 @@ static inline void zynq_init_spi_flashes(uint32_t base_addr, qemu_irq irq, > > static void zynq_init(MachineState *machine) > { > - ram_addr_t ram_size = machine->ram_size; > ARMCPU *cpu; > MemoryRegion *address_space_mem = get_system_memory(); > MemoryRegion *ext_ram = g_new(MemoryRegion, 1); > @@ -168,6 +167,12 @@ static void zynq_init(MachineState *machine) > qemu_irq pic[64]; > int n; > > + /* max 2GB ram */ > + if (machine->ram_size > 0x80000000) { > + error_report("RAM size more than %d is not supported", 0x80000000); Eh? Maybe: if (machine->ram_size > 2 * GiB) { error_report("RAM size more than 2 GiB is not supported"); > + exit(EXIT_FAILURE); > + } > + > cpu = ARM_CPU(object_new(machine->cpu_type)); > > /* By default A9 CPUs have EL3 enabled. This board does not > @@ -184,14 +189,9 @@ static void zynq_init(MachineState *machine) > &error_fatal); > object_property_set_bool(OBJECT(cpu), true, "realized", &error_fatal); > > - /* max 2GB ram */ > - if (ram_size > 0x80000000) { > - ram_size = 0x80000000; > - } > - > /* DDR remapped to address zero. */ > memory_region_allocate_system_memory(ext_ram, NULL, "zynq.ext_ram", > - ram_size); > + machine->ram_size); > memory_region_add_subregion(address_space_mem, 0, ext_ram); > > /* 256K of on-chip memory */ > @@ -300,7 +300,7 @@ static void zynq_init(MachineState *machine) > sysbus_connect_irq(busdev, 0, pic[40 - IRQ_OFFSET]); > sysbus_mmio_map(busdev, 0, 0xF8007000); > > - zynq_binfo.ram_size = ram_size; > + zynq_binfo.ram_size = machine->ram_size; > zynq_binfo.nb_cpus = 1; > zynq_binfo.board_id = 0xd32; > zynq_binfo.loader_start = 0; >