qemu-devel.nongnu.org archive mirror
 help / color / mirror / Atom feed
* Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macronix chips
       [not found] <20180611171518.3390-1-clg@kaod.org>
@ 2018-06-11 17:18 ` Cédric Le Goater
  2018-06-11 22:03   ` Alistair Francis
  0 siblings, 1 reply; 3+ messages in thread
From: Cédric Le Goater @ 2018-06-11 17:18 UTC (permalink / raw)
  To: QEMU Developers
  Cc: qemu-block, Peter Crosthwaite, Alistair Francis, Kevin Wolf,
	Max Reitz, Peter Maydell

On 06/11/2018 07:15 PM, Cédric Le Goater wrote:
> On Macronix chips, two bytes can written to the WRSR. First byte will
> configure the status register and the second the configuration
> register. It is important to save the configuration value as it
> contains the dummy cycle setting when using dual or quad IO mode.
> 
> Signed-off-by: Cédric Le Goater <clg@kaod.org>
> ---
>  hw/block/m25p80.c | 1 +
>  1 file changed, 1 insertion(+)
> 
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index b49c8e9caa04..29775e055a24 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -699,6 +699,7 @@ static void complete_collecting_data(Flash *s)
>          case MAN_MACRONIX:
>              s->quad_enable = extract32(s->data[0], 6, 1);
>              if (s->len > 1) {
> +                s->volatile_cfg = s->data[1];
>                  s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
>              }
>              break;
> 

I sent this patch to qemu-ppc instead of qemu-devel ...

Sorry for the noise.

C. 

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macronix chips
  2018-06-11 17:18 ` [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macronix chips Cédric Le Goater
@ 2018-06-11 22:03   ` Alistair Francis
  2018-06-15 10:44     ` Peter Maydell
  0 siblings, 1 reply; 3+ messages in thread
From: Alistair Francis @ 2018-06-11 22:03 UTC (permalink / raw)
  To: Cédric Le Goater
  Cc: QEMU Developers, Kevin Wolf, Peter Maydell, Qemu-block,
	Peter Crosthwaite, Alistair Francis, Max Reitz

On Mon, Jun 11, 2018 at 10:18 AM, Cédric Le Goater <clg@kaod.org> wrote:
> On 06/11/2018 07:15 PM, Cédric Le Goater wrote:
>> On Macronix chips, two bytes can written to the WRSR. First byte will
>> configure the status register and the second the configuration
>> register. It is important to save the configuration value as it
>> contains the dummy cycle setting when using dual or quad IO mode.
>>
>> Signed-off-by: Cédric Le Goater <clg@kaod.org>

Acked-by: Alistair Francis <alistair.francis@wdc.com>

Alistair

>> ---
>>  hw/block/m25p80.c | 1 +
>>  1 file changed, 1 insertion(+)
>>
>> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
>> index b49c8e9caa04..29775e055a24 100644
>> --- a/hw/block/m25p80.c
>> +++ b/hw/block/m25p80.c
>> @@ -699,6 +699,7 @@ static void complete_collecting_data(Flash *s)
>>          case MAN_MACRONIX:
>>              s->quad_enable = extract32(s->data[0], 6, 1);
>>              if (s->len > 1) {
>> +                s->volatile_cfg = s->data[1];
>>                  s->four_bytes_address_mode = extract32(s->data[1], 5, 1);
>>              }
>>              break;
>>
>
> I sent this patch to qemu-ppc instead of qemu-devel ...
>
> Sorry for the noise.
>
> C.
>

^ permalink raw reply	[flat|nested] 3+ messages in thread

* Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macronix chips
  2018-06-11 22:03   ` Alistair Francis
@ 2018-06-15 10:44     ` Peter Maydell
  0 siblings, 0 replies; 3+ messages in thread
From: Peter Maydell @ 2018-06-15 10:44 UTC (permalink / raw)
  To: Alistair Francis
  Cc: Cédric Le Goater, QEMU Developers, Kevin Wolf, Qemu-block,
	Peter Crosthwaite, Alistair Francis, Max Reitz

On 11 June 2018 at 23:03, Alistair Francis <alistair23@gmail.com> wrote:
> On Mon, Jun 11, 2018 at 10:18 AM, Cédric Le Goater <clg@kaod.org> wrote:
>> On 06/11/2018 07:15 PM, Cédric Le Goater wrote:
>>> On Macronix chips, two bytes can written to the WRSR. First byte will
>>> configure the status register and the second the configuration
>>> register. It is important to save the configuration value as it
>>> contains the dummy cycle setting when using dual or quad IO mode.
>>>
>>> Signed-off-by: Cédric Le Goater <clg@kaod.org>
>
> Acked-by: Alistair Francis <alistair.francis@wdc.com>



Applied to target-arm.next, thanks.

-- PMM

^ permalink raw reply	[flat|nested] 3+ messages in thread

end of thread, other threads:[~2018-06-15 10:45 UTC | newest]

Thread overview: 3+ messages (download: mbox.gz follow: Atom feed
-- links below jump to the message on this page --
     [not found] <20180611171518.3390-1-clg@kaod.org>
2018-06-11 17:18 ` [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for Macronix chips Cédric Le Goater
2018-06-11 22:03   ` Alistair Francis
2018-06-15 10:44     ` Peter Maydell

This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).