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References: <20180611171518.3390-1-clg@kaod.org>
From: =?UTF-8?Q?C=c3=a9dric_Le_Goater?= <clg@kaod.org>
Message-ID: <bfdc313f-f8b0-77a5-e87b-cc9c75f8e110@kaod.org>
Date: Mon, 11 Jun 2018 19:18:06 +0200
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Subject: Re: [Qemu-devel] [PATCH] m25p80: add support for two bytes WRSR for
 Macronix chips
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To: QEMU Developers <qemu-devel@nongnu.org>
Cc: qemu-block@nongnu.org, Peter Crosthwaite <crosthwaite.peter@gmail.com>, Alistair Francis <alistair@alistair23.me>, Kevin Wolf <kwolf@redhat.com>, Max Reitz <mreitz@redhat.com>, Peter Maydell <peter.maydell@linaro.org>

On 06/11/2018 07:15 PM, C=C3=A9dric Le Goater wrote:
> On Macronix chips, two bytes can written to the WRSR. First byte will
> configure the status register and the second the configuration
> register. It is important to save the configuration value as it
> contains the dummy cycle setting when using dual or quad IO mode.
>=20
> Signed-off-by: C=C3=A9dric Le Goater <clg@kaod.org>
> ---
>  hw/block/m25p80.c | 1 +
>  1 file changed, 1 insertion(+)
>=20
> diff --git a/hw/block/m25p80.c b/hw/block/m25p80.c
> index b49c8e9caa04..29775e055a24 100644
> --- a/hw/block/m25p80.c
> +++ b/hw/block/m25p80.c
> @@ -699,6 +699,7 @@ static void complete_collecting_data(Flash *s)
>          case MAN_MACRONIX:
>              s->quad_enable =3D extract32(s->data[0], 6, 1);
>              if (s->len > 1) {
> +                s->volatile_cfg =3D s->data[1];
>                  s->four_bytes_address_mode =3D extract32(s->data[1], 5=
, 1);
>              }
>              break;
>=20

I sent this patch to qemu-ppc instead of qemu-devel ...

Sorry for the noise.

C.=20