hw/ppc/virtex_ml507: Problem with CPU IRQ#3 (PPC40x_INPUT_CINT)

hw/ppc/virtex_ml507: Problem with CPU IRQ#3 (PPC40x_INPUT_CINT)

[Philippe Mathieu-Daudé]

Hi Edgar,

The Xilinx Virtex ML507 model uses 2 different interrupt controllers:
- Universal Interrupt Controller
- Xilinx OPB Interrupt Controller
Both are connected to the same CPU IRQ line, IRQ#3 (PPC40x_INPUT_CINT):

108     uicdev = qdev_new(TYPE_PPC_UIC);
109     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal);
110     object_unref(OBJECT(uicdev));
111     uicsbd = SYS_BUS_DEVICE(uicdev);
112     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
113                        qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT));

240     cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT);
241     dev = qdev_new("xlnx.xps-intc");
242     qdev_prop_set_uint32(dev, "kind-of-intr", 0);
243     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
244     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
245     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);

How is the hardware wired, is it using an OR gate?

I couldn't figure it out looking here:
  * https://docs.xilinx.com/v/u/en-US/ug347
  * 
https://www.xilinx.com/content/dam/xilinx/support/documents/boards_and_kits/ml50x_schematics.pdf

Thanks,

Phil.

Re: hw/ppc/virtex_ml507: Problem with CPU IRQ#3 (PPC40x_INPUT_CINT)

[Edgar E. Iglesias]

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On Tue, Feb 21, 2023 at 7:28 AM Philippe Mathieu-Daudé <philmd@linaro.org>
wrote:

> Hi Edgar,
>
> The Xilinx Virtex ML507 model uses 2 different interrupt controllers:
> - Universal Interrupt Controller
> - Xilinx OPB Interrupt Controller
> Both are connected to the same CPU IRQ line, IRQ#3 (PPC40x_INPUT_CINT):
>
> 108     uicdev = qdev_new(TYPE_PPC_UIC);
> 109     ppc4xx_dcr_realize(PPC4xx_DCR_DEVICE(uicdev), cpu, &error_fatal);
> 110     object_unref(OBJECT(uicdev));
> 111     uicsbd = SYS_BUS_DEVICE(uicdev);
> 112     sysbus_connect_irq(uicsbd, PPCUIC_OUTPUT_INT,
> 113                        qdev_get_gpio_in(DEVICE(cpu),
> PPC40x_INPUT_INT));
>
> 240     cpu_irq = qdev_get_gpio_in(DEVICE(cpu), PPC40x_INPUT_INT);
> 241     dev = qdev_new("xlnx.xps-intc");
> 242     qdev_prop_set_uint32(dev, "kind-of-intr", 0);
> 243     sysbus_realize_and_unref(SYS_BUS_DEVICE(dev), &error_fatal);
> 244     sysbus_mmio_map(SYS_BUS_DEVICE(dev), 0, INTC_BASEADDR);
> 245     sysbus_connect_irq(SYS_BUS_DEVICE(dev), 0, cpu_irq);
>
> How is the hardware wired, is it using an OR gate?
>

Hi Philippe,

I'm not sure if the UIC should be there at all, but I'm not sure.
Either the UIC should go or there should be an OR gate I guess.

The ml507 model was created a little bit empirically trying to get existing
images to run (long time ago).
I don't remember the exact details TBH...

I'll see if I can dig for more details...

Best regards,
Edgar



>
> I couldn't figure it out looking here:
>   * https://docs.xilinx.com/v/u/en-US/ug347
>   *
>
> https://www.xilinx.com/content/dam/xilinx/support/documents/boards_and_kits/ml50x_schematics.pdf
>
> Thanks,
>
> Phil.
>

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