From: Artyom Tarasenko <atar4qemu@gmail.com>
To: qemu-devel@nongnu.org
Cc: Mark Cave-Ayland <mark.cave-ayland@ilande.co.uk>,
Richard Henderson <rth@twiddle.net>,
Artyom Tarasenko <atar4qemu@gmail.com>
Subject: [Qemu-devel] [PATCH v1 24/30] target-sparc: add more registers to dump_mmu
Date: Fri, 4 Nov 2016 21:50:25 +0100 [thread overview]
Message-ID: <c0039806828f2e267305864dbcf28f35e243b890.1478291230.git.atar4qemu@gmail.com> (raw)
In-Reply-To: <cover.1478291230.git.atar4qemu@gmail.com>
In-Reply-To: <cover.1478291230.git.atar4qemu@gmail.com>
Signed-off-by: Artyom Tarasenko <atar4qemu@gmail.com>
Reviewed-by: Richard Henderson <rth@twiddle.net>
---
target-sparc/mmu_helper.c | 2 ++
1 file changed, 2 insertions(+)
diff --git a/target-sparc/mmu_helper.c b/target-sparc/mmu_helper.c
index fa70dc0..8b4664d 100644
--- a/target-sparc/mmu_helper.c
+++ b/target-sparc/mmu_helper.c
@@ -741,6 +741,8 @@ void dump_mmu(FILE *f, fprintf_function cpu_fprintf, CPUSPARCState *env)
PRId64 "\n",
env->dmmu.mmu_primary_context,
env->dmmu.mmu_secondary_context);
+ (*cpu_fprintf)(f, "DMMU Tag Access: %" PRIx64 ", TSB Tag Target: %" PRIx64
+ "\n", env->dmmu.tag_access, env->dmmu.tsb_tag_target);
if ((env->lsu & DMMU_E) == 0) {
(*cpu_fprintf)(f, "DMMU disabled\n");
} else {
--
1.8.3.1
next prev parent reply other threads:[~2016-11-04 20:51 UTC|newest]
Thread overview: 38+ messages / expand[flat|nested] mbox.gz Atom feed top
2016-11-04 20:50 [Qemu-devel] [PATCH v1 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 01/30] target-sparc: ignore MMU-faults if MMU is disabled in hypervisor mode Artyom Tarasenko
2016-11-04 21:19 ` Richard Henderson
2016-11-05 21:20 ` Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 02/30] target-sparc: store cpu super- and hypervisor flags in TB Artyom Tarasenko
2016-11-04 21:21 ` Richard Henderson
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 03/30] target-sparc: use explicit mmu register pointers Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 04/30] target-sparc: add UA2005 TTE bit #defines Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 05/30] target-sparc: add UltraSPARC T1 TLB #defines Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 06/30] target-sparc: on UA2005 don't deliver Interrupt_level_n IRQs in hypervisor mode Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 07/30] target-sparc: simplify replace_tlb_entry by using TTE_PGSIZE Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 08/30] target-sparc: implement UA2005 scratchpad registers Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 09/30] target-sparc: implement UltraSPARC-T1 Strand status ASR Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 10/30] target-sparc: hypervisor mode takes over nucleus mode Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 11/30] target-sparc: implement UA2005 hypervisor traps Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 12/30] target-sparc: implement UA2005 GL register Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 13/30] target-sparc: implement UA2005 rdhpstate and wrhpstate instructions Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 14/30] target-sparc: fix immediate UA2005 traps Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 15/30] target-sparc: use direct address translation in hyperprivileged mode Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 16/30] target-sparc: allow priveleged ASIs " Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 17/30] target-sparc: ignore writes to UA2005 CPU mondo queue register Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 18/30] target-sparc: replace the last tlb entry when no free entries left Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 19/30] target-sparc: use SparcV9MMU type for sparc64 I/D-MMUs Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 20/30] target-sparc: implement UA2005 TSB Pointers Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 21/30] target-sparc: simplify ultrasparc_tsb_pointer Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 22/30] target-sparc: allow 256M sized pages Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 23/30] target-sparc: implement auto-demapping for UA2005 CPUs Artyom Tarasenko
2016-11-04 20:50 ` Artyom Tarasenko [this message]
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 25/30] target-sparc: implement UA2005 ASI_MMU (0x21) Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 27/30] target-sparc: add ST_BLKINIT_ ASIs for UA2005+ CPUs Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 28/30] target-sparc: implement sun4v RTC Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 29/30] target-sparc: move common cpu initialisation routines to sparc64.c Artyom Tarasenko
2016-11-04 20:50 ` [Qemu-devel] [PATCH v1 30/30] target-sparc: fix up niagara machine Artyom Tarasenko
2016-12-15 17:04 ` [Qemu-devel] [PATCH v1 00/30] target-sparc: add niagara OpenSPARC T1 sun4v emulation Artyom Tarasenko
2016-12-30 17:35 ` Mark Cave-Ayland
2017-01-11 16:56 ` Richard Henderson
2017-01-11 17:13 ` Mark Cave-Ayland
2017-01-11 20:33 ` Artyom Tarasenko
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