From: "Philippe Mathieu-Daudé" <philmd@redhat.com>
To: Aleksandar Markovic <aleksandar.markovic@rt-rk.com>,
qemu-devel@nongnu.org
Cc: arikalo@wavecomp.com
Subject: Re: [PATCH 06/11] target/mips: Clean up translate.c
Date: Tue, 24 Sep 2019 15:51:25 +0200 [thread overview]
Message-ID: <c0289668-c1cf-e5b3-567d-46b57e67a65d@redhat.com> (raw)
In-Reply-To: <1569331602-2586-7-git-send-email-aleksandar.markovic@rt-rk.com>
On 9/24/19 3:26 PM, Aleksandar Markovic wrote:
> From: Aleksandar Markovic <amarkovic@wavecomp.com>
>
> Mostly fix errors and warnings reported by 'checkpatch.pl -f'.
>
> Signed-off-by: Aleksandar Markovic <amarkovic@wavecomp.com>
> ---
> target/mips/translate.c | 30 ++++++++++++++++++------------
> 1 file changed, 18 insertions(+), 12 deletions(-)
>
> diff --git a/target/mips/translate.c b/target/mips/translate.c
> index f211995..cc5af2a 100644
> --- a/target/mips/translate.c
> +++ b/target/mips/translate.c
> @@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> tcg_gen_andi_tl(arg, arg, ~0xffff);
> register_name = "BadInstrX";
> break;
> - default:
> + default:
> goto cp0_unimplemented;
> }
> break;
> @@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REG31__KSCRATCH6:
> CP0_CHECK(ctx->kscrexist & (1 << sel));
> tcg_gen_ld_tl(arg, cpu_env,
> - offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
> tcg_gen_ext32s_tl(arg, arg);
> register_name = "KScratch";
> break;
> @@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REG31__KSCRATCH6:
> CP0_CHECK(ctx->kscrexist & (1 << sel));
> tcg_gen_st_tl(arg, cpu_env,
> - offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
> register_name = "KScratch";
> break;
> default:
> @@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> break;
> case CP0_REG01__YQMASK:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMask));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_YQMask));
> register_name = "YQMask";
> break;
> case CP0_REG01__VPESCHEDULE:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPESchedule));
> register_name = "VPESchedule";
> break;
> case CP0_REG01__VPESCHEFBACK:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPEScheFBack));
> register_name = "VPEScheFBack";
> break;
> case CP0_REG01__VPEOPT:
> @@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REGISTER_02:
> switch (sel) {
> case CP0_REG02__ENTRYLO0:
> - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_EntryLo0));
> + tcg_gen_ld_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_EntryLo0));
> register_name = "EntryLo0";
> break;
> case CP0_REG02__TCSTATUS:
> @@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5));
> register_name = "Config5";
> break;
> - /* 6,7 are implementation dependent */
> + /* 6,7 are implementation dependent */
> case CP0_REG16__CONFIG6:
> gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6));
> register_name = "Config6";
> @@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> }
> break;
> case CP0_REGISTER_21:
> - /* Officially reserved, but sel 0 is used for R1x000 framemask */
> + /* Officially reserved, but sel 0 is used for R1x000 framemask */
> CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6));
> switch (sel) {
> case 0:
> @@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> case CP0_REG31__KSCRATCH6:
> CP0_CHECK(ctx->kscrexist & (1 << sel));
> tcg_gen_ld_tl(arg, cpu_env,
> - offsetof(CPUMIPSState, CP0_KScratch[sel-2]));
> + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]));
> register_name = "KScratch";
> break;
> default:
> @@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg, int reg, int sel)
> break;
> case CP0_REG01__VPESCHEDULE:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESchedule));
> + tcg_gen_st_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPESchedule));
> register_name = "VPESchedule";
> break;
> case CP0_REG01__VPESCHEFBACK:
> CP0_CHECK(ctx->insn_flags & ASE_MT);
> - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPEScheFBack));
> + tcg_gen_st_tl(arg, cpu_env,
> + offsetof(CPUMIPSState, CP0_VPEScheFBack));
> register_name = "VPEScheFBack";
> break;
> case CP0_REG01__VPEOPT:
>
Reviewed-by: Philippe Mathieu-Daudé <philmd@redhat.com>
next prev parent reply other threads:[~2019-09-24 14:28 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-09-24 13:26 [PATCH 00/11] target/mips: Misc cleanups for September/October 2019 Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 01/11] target/mips: Clean up helper.c Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 02/11] target/mips: Clean up internal.h Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 03/11] target/mips: Clean up kvm_mips.h Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 04/11] target/mips: Clean up mips-defs.h Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 05/11] target/mips: Clean up op_helper.c Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 06/11] target/mips: Clean up translate.c Aleksandar Markovic
2019-09-24 13:51 ` Philippe Mathieu-Daudé [this message]
2019-09-24 13:26 ` [PATCH 07/11] target/mips: msa: Split helpers for <NLOC|NLZC>.<B|H|W|D> Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 08/11] target/mips: msa: Split helpers for PCNT.<B|H|W|D> Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 09/11] target/mips: msa: Split helpers for BINS<L|R>.<B|H|W|D> Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 10/11] target/mips: msa: Unroll loops and demacro <BMNZ|BMZ|BSEL>.V Aleksandar Markovic
2019-09-24 13:26 ` [PATCH 11/11] target/mips: msa: Split helpers for B<CLR|NEG|SEL>.<B|H|W|D> Aleksandar Markovic
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