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[88.21.68.240]) by smtp.gmail.com with ESMTPSA id b3sm1234968wrw.4.2019.09.24.06.51.26 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Tue, 24 Sep 2019 06:51:26 -0700 (PDT) Subject: Re: [PATCH 06/11] target/mips: Clean up translate.c To: Aleksandar Markovic , qemu-devel@nongnu.org References: <1569331602-2586-1-git-send-email-aleksandar.markovic@rt-rk.com> <1569331602-2586-7-git-send-email-aleksandar.markovic@rt-rk.com> From: =?UTF-8?Q?Philippe_Mathieu-Daud=c3=a9?= Openpgp: id=89C1E78F601EE86C867495CBA2A3FD6EDEADC0DE; url=http://pgp.mit.edu/pks/lookup?op=get&search=0xA2A3FD6EDEADC0DE Message-ID: Date: Tue, 24 Sep 2019 15:51:25 +0200 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.7.0 MIME-Version: 1.0 In-Reply-To: <1569331602-2586-7-git-send-email-aleksandar.markovic@rt-rk.com> Content-Language: en-US X-MC-Unique: mU93WWGEOieD6aC_hdrD8Q-1 X-Mimecast-Spam-Score: 0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-detected-operating-system: by eggs.gnu.org: GNU/Linux 2.2.x-3.x [generic] X-Received-From: 207.211.31.81 X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.23 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Cc: arikalo@wavecomp.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: "Qemu-devel" On 9/24/19 3:26 PM, Aleksandar Markovic wrote: > From: Aleksandar Markovic >=20 > Mostly fix errors and warnings reported by 'checkpatch.pl -f'. >=20 > Signed-off-by: Aleksandar Markovic > --- > target/mips/translate.c | 30 ++++++++++++++++++------------ > 1 file changed, 18 insertions(+), 12 deletions(-) >=20 > diff --git a/target/mips/translate.c b/target/mips/translate.c > index f211995..cc5af2a 100644 > --- a/target/mips/translate.c > +++ b/target/mips/translate.c > @@ -7118,7 +7118,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) > tcg_gen_andi_tl(arg, arg, ~0xffff); > register_name =3D "BadInstrX"; > break; > - default: > + default: > goto cp0_unimplemented; > } > break; > @@ -7545,7 +7545,7 @@ static void gen_mfc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) > case CP0_REG31__KSCRATCH6: > CP0_CHECK(ctx->kscrexist & (1 << sel)); > tcg_gen_ld_tl(arg, cpu_env, > - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); > + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]))= ; > tcg_gen_ext32s_tl(arg, arg); > register_name =3D "KScratch"; > break; > @@ -8295,7 +8295,7 @@ static void gen_mtc0(DisasContext *ctx, TCGv arg, i= nt reg, int sel) > case CP0_REG31__KSCRATCH6: > CP0_CHECK(ctx->kscrexist & (1 << sel)); > tcg_gen_st_tl(arg, cpu_env, > - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); > + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]))= ; > register_name =3D "KScratch"; > break; > default: > @@ -8387,17 +8387,20 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg= , int reg, int sel) > break; > case CP0_REG01__YQMASK: > CP0_CHECK(ctx->insn_flags & ASE_MT); > - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_YQMas= k)); > + tcg_gen_ld_tl(arg, cpu_env, > + offsetof(CPUMIPSState, CP0_YQMask)); > register_name =3D "YQMask"; > break; > case CP0_REG01__VPESCHEDULE: > CP0_CHECK(ctx->insn_flags & ASE_MT); > - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESc= hedule)); > + tcg_gen_ld_tl(arg, cpu_env, > + offsetof(CPUMIPSState, CP0_VPESchedule)); > register_name =3D "VPESchedule"; > break; > case CP0_REG01__VPESCHEFBACK: > CP0_CHECK(ctx->insn_flags & ASE_MT); > - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESc= heFBack)); > + tcg_gen_ld_tl(arg, cpu_env, > + offsetof(CPUMIPSState, CP0_VPEScheFBack)); > register_name =3D "VPEScheFBack"; > break; > case CP0_REG01__VPEOPT: > @@ -8412,7 +8415,8 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) > case CP0_REGISTER_02: > switch (sel) { > case CP0_REG02__ENTRYLO0: > - tcg_gen_ld_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_Entry= Lo0)); > + tcg_gen_ld_tl(arg, cpu_env, > + offsetof(CPUMIPSState, CP0_EntryLo0)); > register_name =3D "EntryLo0"; > break; > case CP0_REG02__TCSTATUS: > @@ -8756,7 +8760,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) > gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config5)); > register_name =3D "Config5"; > break; > - /* 6,7 are implementation dependent */ > + /* 6,7 are implementation dependent */ > case CP0_REG16__CONFIG6: > gen_mfc0_load32(arg, offsetof(CPUMIPSState, CP0_Config6)); > register_name =3D "Config6"; > @@ -8837,7 +8841,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) > } > break; > case CP0_REGISTER_21: > - /* Officially reserved, but sel 0 is used for R1x000 framemask */ > + /* Officially reserved, but sel 0 is used for R1x000 framemask *= / > CP0_CHECK(!(ctx->insn_flags & ISA_MIPS32R6)); > switch (sel) { > case 0: > @@ -9022,7 +9026,7 @@ static void gen_dmfc0(DisasContext *ctx, TCGv arg, = int reg, int sel) > case CP0_REG31__KSCRATCH6: > CP0_CHECK(ctx->kscrexist & (1 << sel)); > tcg_gen_ld_tl(arg, cpu_env, > - offsetof(CPUMIPSState, CP0_KScratch[sel-2])); > + offsetof(CPUMIPSState, CP0_KScratch[sel - 2]))= ; > register_name =3D "KScratch"; > break; > default: > @@ -9112,12 +9116,14 @@ static void gen_dmtc0(DisasContext *ctx, TCGv arg= , int reg, int sel) > break; > case CP0_REG01__VPESCHEDULE: > CP0_CHECK(ctx->insn_flags & ASE_MT); > - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESc= hedule)); > + tcg_gen_st_tl(arg, cpu_env, > + offsetof(CPUMIPSState, CP0_VPESchedule)); > register_name =3D "VPESchedule"; > break; > case CP0_REG01__VPESCHEFBACK: > CP0_CHECK(ctx->insn_flags & ASE_MT); > - tcg_gen_st_tl(arg, cpu_env, offsetof(CPUMIPSState, CP0_VPESc= heFBack)); > + tcg_gen_st_tl(arg, cpu_env, > + offsetof(CPUMIPSState, CP0_VPEScheFBack)); > register_name =3D "VPEScheFBack"; > break; > case CP0_REG01__VPEOPT: >=20 Reviewed-by: Philippe Mathieu-Daud=C3=A9