From: Jan Bobek <jan.bobek@gmail.com>
To: Richard Henderson <richard.henderson@linaro.org>, qemu-devel@nongnu.org
Cc: "Alex Bennée" <alex.bennee@linaro.org>
Subject: Re: [Qemu-devel] [RISU PATCH v3 04/18] risugen_x86_constraints: add module
Date: Sun, 14 Jul 2019 18:39:20 -0400 [thread overview]
Message-ID: <c0598465-4283-6451-c15c-e55fcb199ced@gmail.com> (raw)
In-Reply-To: <e64091a9-d8f4-a71c-fcbd-ac27d85d2e64@linaro.org>
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On 7/12/19 10:24 AM, Richard Henderson wrote:
> On 7/12/19 12:32 AM, Jan Bobek wrote:
>> +sub vex($%)
>> +{
>> + my ($insn, %vex) = @_;
>> + my $regidw = $is_x86_64 ? 4 : 3;
>> +
>> + # There is no point in randomizing other VEX fields, since
>> + # VEX.R/.X/.B are encoded automatically by risugen_x86_asm, and
>> + # VEX.M/.P are opcodes.
>> + $vex{l} = randint(width => 1) ? 256 : 128 unless defined $vex{l};
>
> VEX.L is sort-of opcode-like as well. It certainly differentiates AVX1 vs
> AVX2, and so probably should be constrained somehow. I can't think of what's
> the best way to do that at the moment, since our existing --xstate=foo isn't right.
>
> Perhaps just a FIXME comment for now?
So, the instructions that use VEX.L specify it in the !constraints
block in the config file. Originally, I thought some instructions are
supposed to ignore it (denoted by LIG in the Intel manual -- it's the
scalar instructions like ADDSS), so it might be worth randomizing.
However, when I later read the manual pages of some of these
instructions, it said they are supposed to be encoded with VEX.L=0
anyway. I didn't check every single one of them, but right now they
are all encoded with VEX.L=0, so I suppose this line can be removed
and we can rely on the caller (the !constraints block) to always
specify it.
>> +sub modrm_($%)
>> +{
>> + my ($insn, %args) = @_;
>> + my $regidw = $is_x86_64 ? 4 : 3;
>> +
>> + my %modrm = ();
>> + if (defined $args{reg}) {
>> + # This makes the config file syntax a bit more accommodating
>> + # in cases where MODRM.REG is an opcode extension field.
>> + $modrm{reg} = $args{reg};
>> + } else {
>> + $modrm{reg} = randint(width => $regidw);
>> + }
>> +
>> + # There is also a displacement-only form, but we don't know
>> + # absolute address of the memblock, so we cannot test it.
>
> 32-bit mode has displacement-only, aka absolute; 64-bit replaces that with
> rip-relative. But agreed that the first is impossible to test and the second
> is difficult.
>
>> +sub modrm($%)
>> +{
>> + my ($insn, %args) = @_;
>> + modrm_($insn, indexk => 'index', %args);
>> +}
>
> How are you avoiding %rsp as index?
> I saw you die for that in the previous patch...
See write_mem_getoffset in risugen_x86.pm. I felt there's a better
place for it there, since that's when we actually need to write to it,
so the problem is more exposed.
-Jan
>
> r~
>
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next prev parent reply other threads:[~2019-07-14 22:39 UTC|newest]
Thread overview: 49+ messages / expand[flat|nested] mbox.gz Atom feed top
2019-07-11 22:32 [Qemu-devel] [RISU PATCH v3 00/18] Support for generating x86 SIMD test images Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 01/18] risugen_common: add helper functions insnv, randint Jan Bobek
2019-07-12 5:48 ` Richard Henderson
2019-07-14 21:55 ` Jan Bobek
2019-07-12 12:41 ` Alex Bennée
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 02/18] risugen_common: split eval_with_fields into extract_fields and eval_block Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 03/18] risugen_x86_asm: add module Jan Bobek
2019-07-12 14:11 ` Richard Henderson
2019-07-14 22:04 ` Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 04/18] risugen_x86_constraints: " Jan Bobek
2019-07-12 14:24 ` Richard Henderson
2019-07-14 22:39 ` Jan Bobek [this message]
2019-07-21 1:54 ` Richard Henderson
2019-07-22 13:41 ` Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 05/18] risugen_x86_memory: " Jan Bobek
2019-07-21 1:58 ` Richard Henderson
2019-07-22 13:53 ` Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 06/18] risugen_x86: " Jan Bobek
2019-07-21 2:02 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 07/18] risugen: allow all byte-aligned instructions Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 08/18] risugen: add command-line flag --x86_64 Jan Bobek
2019-07-17 17:00 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 09/18] risugen: add --xfeatures option for x86 Jan Bobek
2019-07-17 17:01 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 10/18] x86.risu: add MMX instructions Jan Bobek
2019-07-20 4:30 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 11/18] x86.risu: add SSE instructions Jan Bobek
2019-07-20 17:50 ` Richard Henderson
2019-07-22 13:57 ` Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 12/18] x86.risu: add SSE2 instructions Jan Bobek
2019-07-20 21:19 ` Richard Henderson
2019-07-22 14:12 ` Jan Bobek
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 13/18] x86.risu: add SSE3 instructions Jan Bobek
2019-07-20 21:27 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 14/18] x86.risu: add SSSE3 instructions Jan Bobek
2019-07-20 21:52 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 15/18] x86.risu: add SSE4.1 and SSE4.2 instructions Jan Bobek
2019-07-20 22:28 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 16/18] x86.risu: add AES and PCLMULQDQ instructions Jan Bobek
2019-07-20 22:35 ` Richard Henderson
2019-07-11 22:32 ` [Qemu-devel] [RISU PATCH v3 17/18] x86.risu: add AVX instructions Jan Bobek
2019-07-21 0:04 ` Richard Henderson
2019-07-22 14:23 ` Jan Bobek
2019-07-11 22:33 ` [Qemu-devel] [RISU PATCH v3 18/18] x86.risu: add AVX2 instructions Jan Bobek
2019-07-21 0:46 ` Richard Henderson
2019-07-22 14:41 ` Jan Bobek
2019-07-12 13:34 ` [Qemu-devel] [RISU PATCH v3 00/18] Support for generating x86 SIMD test images Alex Bennée
2019-07-14 23:08 ` Jan Bobek
2019-07-15 10:14 ` Alex Bennée
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