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([2a01:e0a:f0e:9070:527b:9dff:feef:3874]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-3997f9a3f2asm19488557f8f.30.2025.03.27.02.11.53 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Thu, 27 Mar 2025 02:11:53 -0700 (PDT) Message-ID: Date: Thu, 27 Mar 2025 10:11:52 +0100 MIME-Version: 1.0 User-Agent: Mozilla Thunderbird Subject: Re: [RFC PATCH v2 17/20] hw/arm/smmuv3: Check idr registers for STE_S1CDMAX and STE_S1STALLD Content-Language: en-US To: Shameerali Kolothum Thodi , Nicolin Chen Cc: "qemu-arm@nongnu.org" , "qemu-devel@nongnu.org" , "peter.maydell@linaro.org" , "jgg@nvidia.com" , "ddutile@redhat.com" , "berrange@redhat.com" , "nathanc@nvidia.com" , "mochs@nvidia.com" , "smostafa@google.com" , Linuxarm , "Wangzhou (B)" , jiangkunkun , Jonathan Cameron , "zhangfei.gao@linaro.org" References: <20250311141045.66620-1-shameerali.kolothum.thodi@huawei.com> <20250311141045.66620-18-shameerali.kolothum.thodi@huawei.com> <477323cb-12d3-484c-8ad9-61229ede3efe@redhat.com> From: Eric Auger In-Reply-To: Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=eric.auger@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -20 X-Spam_score: -2.1 X-Spam_bar: -- X-Spam_report: (-2.1 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.001, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H2=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=unavailable autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Reply-To: eric.auger@redhat.com Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Hi, On 3/27/25 8:54 AM, Shameerali Kolothum Thodi wrote: > >> -----Original Message----- >> From: Nicolin Chen >> Sent: Wednesday, March 26, 2025 7:47 PM >> To: Eric Auger >> Cc: Shameerali Kolothum Thodi >> ; qemu-arm@nongnu.org; >> qemu-devel@nongnu.org; peter.maydell@linaro.org; jgg@nvidia.com; >> ddutile@redhat.com; berrange@redhat.com; nathanc@nvidia.com; >> mochs@nvidia.com; smostafa@google.com; Linuxarm >> ; Wangzhou (B) ; >> jiangkunkun ; Jonathan Cameron >> ; zhangfei.gao@linaro.org >> Subject: Re: [RFC PATCH v2 17/20] hw/arm/smmuv3: Check idr registers for >> STE_S1CDMAX and STE_S1STALLD >> >>> Again I think we need to understand the consequence of having a more >>> comprehensive support of SSID. This also holds with old the IDR fields >>> that may be inherited from the HW and we don't support yet in the >>> emulation code >> To support guest-level SVA, it must support SSID. We can keep the >> SSIDSIZE=0 in an emulated SMMU. Would you elaborate the concern of >> doing so? I just want to make sure we dissociate both accel and emulated paths and we do not advertise SSID in one mode while we do not fully support it. >> > Regarding adding support for SSID/SVA in emulation code, the support also depends on > device PRI/IOPF feature as well. Do we have any emulated devices that can make use > this? I would say we can add that support later if there is any real use cases for that. x86 may be ahead of us in this area. Maybe this was tested by Zhenzhong when contributing emulation for S1 support in intel_iommu? Eric > > Thanks, > Shameer