From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:48449) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCUNr-0001Fv-Th for qemu-devel@nongnu.org; Mon, 13 Jun 2016 12:06:40 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1bCUNl-0003WR-Py for qemu-devel@nongnu.org; Mon, 13 Jun 2016 12:06:38 -0400 Received: from mail-qg0-x233.google.com ([2607:f8b0:400d:c04::233]:33935) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1bCUNl-0003WL-LN for qemu-devel@nongnu.org; Mon, 13 Jun 2016 12:06:33 -0400 Received: by mail-qg0-x233.google.com with SMTP id p34so70645271qgp.1 for ; Mon, 13 Jun 2016 09:06:33 -0700 (PDT) Sender: Richard Henderson References: <1465758111-60131-1-git-send-email-mrolnik@gmail.com> <1465758111-60131-9-git-send-email-mrolnik@gmail.com> From: Richard Henderson Message-ID: Date: Mon, 13 Jun 2016 09:06:29 -0700 MIME-Version: 1.0 In-Reply-To: <1465758111-60131-9-git-send-email-mrolnik@gmail.com> Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH v6 08/11] target-avr: adding instruction translation List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Michael Rolnik , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org On 06/12/2016 12:01 PM, Michael Rolnik wrote: > +void gen_push_ret(CPUAVRState *env, int ret) > +{ > + if (avr_feature(env, AVR_FEATURE_1_BYTE_PC)) { > + > + TCGv t0 = tcg_const_i32((ret & 0x0000ff)); > + > + tcg_gen_qemu_st8(t0, cpu_sp, MMU_DATA_IDX); > + tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); > + > + tcg_temp_free_i32(t0); > + } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { > + > + TCGv t0 = tcg_const_i32((ret & 0x00ffff)); > + > + tcg_gen_qemu_st16(t0, cpu_sp, MMU_DATA_IDX); > + tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); This stores to the wrong bytes. You need tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); tcg_gen_qemu_st_tl(t0, cpu_sp, MMU_DATA_IDX, MO_BEUW); tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); > + } else if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { > + > + TCGv t0 = tcg_const_i32((ret & 0x0000ff)); > + TCGv t1 = tcg_const_i32((ret & 0xffff00) >> 8); > + > + tcg_gen_qemu_st8(t0, cpu_sp, MMU_DATA_IDX); > + tcg_gen_subi_tl(cpu_sp, cpu_sp, 1); > + > + tcg_gen_qemu_st16(t1, cpu_sp, MMU_DATA_IDX); > + tcg_gen_subi_tl(cpu_sp, cpu_sp, 2); Similarly. > +void gen_pop_ret(CPUAVRState *env, TCGv ret) > +{ > + if (avr_feature(env, AVR_FEATURE_1_BYTE_PC)) { > + > + tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); > + tcg_gen_qemu_ld8u(ret, cpu_sp, MMU_DATA_IDX); > + } else if (avr_feature(env, AVR_FEATURE_2_BYTE_PC)) { > + > + tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); > + tcg_gen_qemu_ld16u(ret, cpu_sp, MMU_DATA_IDX); Similarly, tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); > + } else if (avr_feature(env, AVR_FEATURE_3_BYTE_PC)) { > + > + TCGv t0 = tcg_temp_new_i32(); > + > + tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); > + tcg_gen_qemu_ld8u(ret, cpu_sp, MMU_DATA_IDX); > + > + tcg_gen_addi_tl(cpu_sp, cpu_sp, 2); > + tcg_gen_qemu_ld16u(t0, cpu_sp, MMU_DATA_IDX); > + > + tcg_gen_shli_tl(t0, t0, 16); > + tcg_gen_or_tl(ret, ret, t0); You're putting t0 at the wrong end. tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); tcg_gen_qemu_ld_tl(t0, cpu_sp, MMU_DATA_IDX, MO_UB); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); tcg_gen_qemu_ld_tl(ret, cpu_sp, MMU_DATA_IDX, MO_BEUW); tcg_gen_addi_tl(cpu_sp, cpu_sp, 1); tcg_gen_deposit_tl(ret, ret, t0, 16, 8); r~