From: Thomas Huth <thuth@redhat.com>
To: Daniel Henrique Barboza <dbarboza@ventanamicro.com>,
Peter Maydell <peter.maydell@linaro.org>
Cc: Alistair Francis <alistair23@gmail.com>,
qemu-devel@nongnu.org,
Alistair Francis <alistair.francis@wdc.com>
Subject: Re: [PULL v2 00/47] riscv-to-apply queue
Date: Mon, 30 Sep 2024 13:35:00 +0200 [thread overview]
Message-ID: <c09f8552-7362-4fb8-a072-37dd03dbdfa5@redhat.com> (raw)
In-Reply-To: <7d60d882-3b59-428d-b63e-7d7444bd96fa@redhat.com>
On 30/09/2024 12.58, Thomas Huth wrote:
> On 29/09/2024 22.53, Daniel Henrique Barboza wrote:
>>
>>
>> On 9/29/24 12:38 PM, Peter Maydell wrote:
>>> On Sat, 28 Sept 2024 at 21:40, Daniel Henrique Barboza
>>> <dbarboza@ventanamicro.com> wrote:
>>>>
>>>>
>>>>
>>>> On 9/28/24 8:34 AM, Peter Maydell wrote:
>>>>> The assertion failure is
>>>>> ERROR:../tests/qtest/riscv-iommu-test.c:72:test_reg_reset: assertion
>>>>> failed (cap & RISCV_IOMMU_CAP_VERSION == 0x10): (0 == 16)
>>>>
>>>> The root cause is that the qtests I added aren't considering the
>>>> endianess of the
>>>> host. The RISC-V IOMMU is being implemented as LE only and all regs are
>>>> being
>>>> read/written in memory as LE. The qtest read/write helpers must take the
>>>> qtest
>>>> endianess into account. We make this type of handling in other qtest
>>>> archs like
>>>> ppc64.
>>>>
>>>> I have a fix for the tests but I'm unable to run the ubuntu-22.04-s390x-
>>>> all-system
>>>> job to verify it, even after setting Cirrus like Thomas taught me a week
>>>> ago. In
>>>> fact I have no 'ubuntu-22-*' jobs available to run.
>>>
>>> It's on the private s390 VM we have, so it's set up only to
>>> be available on the main CI run (there's not enough capacity
>>> on the machine to do any more than that). If you want to point
>>> me at a gitlab branch I can do a quick "make check" on that
>>> if you like.
>>
>> I appreciate it. This is the repo:
>>
>> https://gitlab.com/danielhb/qemu/-/tree/pull_fix
>>
>> If this is enough to fix the tests, I'll amend it in the new IOMMU version.
>> If we still failing then I'll need to set this s390 VM.
>>
>> By the way, if you have any recipe/pointers to set this s390 VM to share,
>> that would be great.
>
> You can also use Travis-CI for testing QEMU on a s390x host, see e.g. my
> runs here:
>
> https://app.travis-ci.com/github/huth/qemu
... apart from the fact, that it currently seems to be completely broken
again :-( ... I guess that means: Never mind, sorry for the distraction!
Thomas
next prev parent reply other threads:[~2024-09-30 11:35 UTC|newest]
Thread overview: 68+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-09-24 22:17 [PULL v2 00/47] riscv-to-apply queue Alistair Francis
2024-09-24 22:17 ` [PULL v2 01/47] target/riscv: Add a property to set vl to ceil(AVL/2) Alistair Francis
2024-09-24 22:17 ` [PULL v2 02/47] tests/acpi: Add empty ACPI SRAT data file for RISC-V Alistair Francis
2024-09-24 22:17 ` [PULL v2 03/47] tests/qtest/bios-tables-test.c: Enable numamem testing " Alistair Francis
2024-09-24 22:17 ` [PULL v2 04/47] tests/acpi: Add expected ACPI SRAT AML file " Alistair Francis
2024-09-24 22:17 ` [PULL v2 05/47] target/riscv/tcg/tcg-cpu.c: consider MISA bit choice in implied rule Alistair Francis
2024-09-24 22:17 ` [PULL v2 06/47] target/riscv: fix za64rs enabling Alistair Francis
2024-09-24 22:17 ` [PULL v2 07/47] target: riscv: Enable Bit Manip for OpenTitan Ibex CPU Alistair Francis
2024-09-24 22:17 ` [PULL v2 08/47] target/riscv/kvm: Fix the group bit setting of AIA Alistair Francis
2024-09-24 22:17 ` [PULL v2 09/47] target/riscv: Stop timer with infinite timecmp Alistair Francis
2024-09-24 22:17 ` [PULL v2 10/47] target/riscv/cpu.c: Add 'fcsr' register to QEMU log as a part of F extension Alistair Francis
2024-09-24 22:17 ` [PULL v2 11/47] util/util/cpuinfo-riscv.c: fix riscv64 build on musl libc Alistair Francis
2024-09-24 22:17 ` [PULL v2 12/47] target/riscv: Preliminary textra trigger CSR writting support Alistair Francis
2024-09-24 22:17 ` [PULL v2 13/47] target/riscv: Add textra matching condition for the triggers Alistair Francis
2024-09-24 22:17 ` [PULL v2 14/47] exec/memtxattr: add process identifier to the transaction attributes Alistair Francis
2024-09-24 22:17 ` [PULL v2 15/47] hw/riscv: add riscv-iommu-bits.h Alistair Francis
2024-09-24 22:17 ` [PULL v2 16/47] hw/riscv: add RISC-V IOMMU base emulation Alistair Francis
2024-09-28 20:22 ` Peter Maydell
2024-09-28 21:01 ` Daniel Henrique Barboza
2024-09-29 15:46 ` Peter Maydell
2024-10-01 22:14 ` Tomasz Jeznach
2024-10-01 23:00 ` Daniel Henrique Barboza
2024-10-01 23:19 ` Tomasz Jeznach
2024-10-01 22:24 ` Tomasz Jeznach
2024-10-01 23:15 ` Daniel Henrique Barboza
2024-09-24 22:17 ` [PULL v2 17/47] pci-ids.rst: add Red Hat pci-id for RISC-V IOMMU device Alistair Francis
2024-09-24 22:17 ` [PULL v2 18/47] hw/riscv: add riscv-iommu-pci reference device Alistair Francis
2024-09-24 22:17 ` [PULL v2 19/47] hw/riscv/virt.c: support for RISC-V IOMMU PCIDevice hotplug Alistair Francis
2024-09-24 22:17 ` [PULL v2 20/47] test/qtest: add riscv-iommu-pci tests Alistair Francis
2024-09-24 22:17 ` [PULL v2 21/47] hw/riscv/riscv-iommu: add Address Translation Cache (IOATC) Alistair Francis
2024-09-24 22:17 ` [PULL v2 22/47] hw/riscv/riscv-iommu: add ATS support Alistair Francis
2024-09-24 22:17 ` [PULL v2 23/47] hw/riscv/riscv-iommu: add DBG support Alistair Francis
2024-09-24 22:17 ` [PULL v2 24/47] qtest/riscv-iommu-test: add init queues test Alistair Francis
2024-09-24 22:17 ` [PULL v2 25/47] docs/specs: add riscv-iommu Alistair Francis
2024-09-24 22:17 ` [PULL v2 26/47] hw/riscv: Respect firmware ELF entry point Alistair Francis
2024-09-24 22:17 ` [PULL v2 27/47] target: riscv: Add Svvptc extension support Alistair Francis
2024-09-24 22:17 ` [PULL v2 28/47] target/riscv32: Fix masking of physical address Alistair Francis
2024-09-24 22:17 ` [PULL v2 29/47] target/riscv/cpu_helper: Fix linking problem with semihosting disabled Alistair Francis
2024-09-24 22:17 ` [PULL v2 30/47] hw/intc: riscv-imsic: Fix interrupt state updates Alistair Francis
2024-09-24 22:17 ` [PULL v2 31/47] bsd-user: Implement RISC-V CPU initialization and main loop Alistair Francis
2024-09-24 22:17 ` [PULL v2 32/47] bsd-user: Add RISC-V CPU execution loop and syscall handling Alistair Francis
2024-09-24 22:17 ` [PULL v2 33/47] bsd-user: Implement RISC-V CPU register cloning and reset functions Alistair Francis
2024-09-24 22:17 ` [PULL v2 34/47] bsd-user: Implement RISC-V TLS register setup Alistair Francis
2024-09-24 22:17 ` [PULL v2 35/47] bsd-user: Add RISC-V ELF definitions and hardware capability detection Alistair Francis
2024-09-24 22:17 ` [PULL v2 36/47] bsd-user: Define RISC-V register structures and register copying Alistair Francis
2024-09-24 22:17 ` [PULL v2 37/47] bsd-user: Add RISC-V signal trampoline setup function Alistair Francis
2024-09-24 22:17 ` [PULL v2 38/47] bsd-user: Implement RISC-V sysarch system call emulation Alistair Francis
2024-09-24 22:17 ` [PULL v2 39/47] bsd-user: Add RISC-V thread setup and initialization support Alistair Francis
2024-09-24 22:17 ` [PULL v2 40/47] bsd-user: Define RISC-V VM parameters and helper functions Alistair Francis
2024-09-24 22:17 ` [PULL v2 41/47] bsd-user: Define RISC-V system call structures and constants Alistair Francis
2024-09-24 22:17 ` [PULL v2 42/47] bsd-user: Add generic RISC-V64 target definitions Alistair Francis
2024-09-24 22:17 ` [PULL v2 43/47] bsd-user: Define RISC-V signal handling structures and constants Alistair Francis
2024-09-24 22:17 ` [PULL v2 44/47] bsd-user: Implement RISC-V signal trampoline setup functions Alistair Francis
2024-09-24 22:17 ` [PULL v2 45/47] bsd-user: Implement 'get_mcontext' for RISC-V Alistair Francis
2024-09-24 22:17 ` [PULL v2 46/47] bsd-user: Implement set_mcontext and get_ucontext_sigreturn for RISCV Alistair Francis
2024-09-24 22:17 ` [PULL v2 47/47] bsd-user: Add RISC-V 64-bit Target Configuration and Debug XML Files Alistair Francis
2024-09-28 11:34 ` [PULL v2 00/47] riscv-to-apply queue Peter Maydell
2024-09-28 20:23 ` Peter Maydell
2024-09-28 20:40 ` Daniel Henrique Barboza
2024-09-29 15:38 ` Peter Maydell
2024-09-29 20:53 ` Daniel Henrique Barboza
2024-09-30 10:48 ` Peter Maydell
2024-09-30 12:05 ` Daniel Henrique Barboza
2024-09-30 10:58 ` Thomas Huth
2024-09-30 11:35 ` Thomas Huth [this message]
2024-10-21 16:17 ` Thomas Huth
2024-09-30 12:10 ` Ilya Leoshkevich
2024-09-30 23:04 ` Daniel Henrique Barboza
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=c09f8552-7362-4fb8-a072-37dd03dbdfa5@redhat.com \
--to=thuth@redhat.com \
--cc=alistair.francis@wdc.com \
--cc=alistair23@gmail.com \
--cc=dbarboza@ventanamicro.com \
--cc=peter.maydell@linaro.org \
--cc=qemu-devel@nongnu.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox;
as well as URLs for NNTP newsgroup(s).