From: Richard Henderson <richard.henderson@linaro.org>
To: Deepak Gupta <debug@rivosinc.com>,
qemu-riscv@nongnu.org, qemu-devel@nongnu.org
Cc: palmer@dabbelt.com, Alistair.Francis@wdc.com, bmeng.cn@gmail.com,
liwei1518@gmail.com, dbarboza@ventanamicro.com,
zhiwei_liu@linux.alibaba.com, jim.shu@sifive.com,
andy.chiu@sifive.com, kito.cheng@sifive.com
Subject: Re: [PATCH v5 11/15] target/riscv: mmu changes for zicfiss shadow stack protection
Date: Tue, 20 Aug 2024 19:20:48 +1000 [thread overview]
Message-ID: <c0afdd87-71c1-4b02-a2fb-5c9349205d8f@linaro.org> (raw)
In-Reply-To: <ZsRHPDG/GkyhdrQi@debug.ba.rivosinc.com>
On 8/20/24 17:35, Deepak Gupta wrote:
>> + /* If shadow stack instruction initiated this access, treat it as store */
>> + if (mmu_idx & MMU_IDX_SS_WRITE) {
>> + access_type = MMU_DATA_STORE;
>> + }
>> +
>
> I think I forgot to address this. Do you still want me to fix this up like you
> had suggested?
Yes, this still needs fixing.
> IIRC, you mentioned to use TARGET_INSN_START_EXTRA_WORDS=2. Honestly I don't know
> what it means and how its used. Based on git grep and some readup, are you expecting
> something
> along the below lines?
>
>
> """
>
> diff --git a/target/riscv/cpu.h b/target/riscv/cpu.h
> index fee31b8037..dfd2efa941 100644
> --- a/target/riscv/cpu.h
> +++ b/target/riscv/cpu.h
> @@ -47,7 +47,7 @@ typedef struct CPUArchState CPURISCVState;
> * RISC-V-specific extra insn start words:
> * 1: Original instruction opcode
> */
> -#define TARGET_INSN_START_EXTRA_WORDS 1
> +#define TARGET_INSN_START_EXTRA_WORDS 2
>
> #define RV(x) ((target_ulong)1 << (x - 'A'))
>
> diff --git a/target/riscv/cpu_helper.c b/target/riscv/cpu_helper.c
> index f74a1216b1..b266177e46 100644
> --- a/target/riscv/cpu_helper.c
> +++ b/target/riscv/cpu_helper.c
> @@ -1271,6 +1271,11 @@ static void raise_mmu_exception(CPURISCVState *env, target_ulong
> address,
> {
> CPUState *cs = env_cpu(env);
>
> + if (!pmp_violation &&
> + tcg_ctx->gen_insn_data[TARGET_INSN_START_EXTRA_WORDS-1] & 1) {
> + tcg_ctx->gen_insn_data[TARGET_INSN_START_EXTRA_WORDS-1] &= ~1;
> + access_type = MMU_DATA_STORE;
> + }
The first thing to understand is that the unwind data is stored by the compiler and
recovered by the unwinder.
The unwind data is exposed to the target via one of two methods:
(1) TCGCPUOps.restore_state_to_opc, i.e. riscv_restore_state_to_opc.
The data[] argument contains the extra words.
With this method, the extra words are restored to env and are
available in a later call to riscv_cpu_do_interrupt.
Compare env->bins from the first extra word, which is used exactly so.
This is probably the easiest and best option.
You'd promote LOAD* to STORE_AMO* while dispatching the interrupt.
(2) cpu_unwind_state_data()
With this method, you have immediate access to the extra words,
and don't need to store them anywhere else.
This is supposed to be used when we are *not* going to raise
an exception, merely look something up and continue execution.
Otherwise, we'd be performing the unwind operation twice,
and it's not cheap.
So, tcg_ctx->gen_insn_data[] is not something you'd ever touch,
and this is the wrong spot to do anything.
r~
next prev parent reply other threads:[~2024-08-20 9:21 UTC|newest]
Thread overview: 25+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-20 0:01 [PATCH v5 00/15] riscv support for control flow integrity extensions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 01/15] target/riscv: Add zicfilp extension Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 02/15] target/riscv: Introduce elp state and enabling controls for zicfilp Deepak Gupta
2024-08-20 5:17 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 03/15] target/riscv: save and restore elp state on priv transitions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 04/15] target/riscv: additional code information for sw check Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 05/15] target/riscv: tracking indirect branches (fcfi) for zicfilp Deepak Gupta
2024-08-20 5:24 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 06/15] target/riscv: zicfilp `lpad` impl and branch tracking Deepak Gupta
2024-08-20 5:29 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 07/15] disas/riscv: enable `lpad` disassembly Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 08/15] target/riscv: Add zicfiss extension Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 09/15] target/riscv: introduce ssp and enabling controls for zicfiss Deepak Gupta
2024-08-20 5:34 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 10/15] target/riscv: tb flag for shadow stack instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 11/15] target/riscv: mmu changes for zicfiss shadow stack protection Deepak Gupta
2024-08-20 7:35 ` Deepak Gupta
2024-08-20 9:20 ` Richard Henderson [this message]
2024-08-20 18:55 ` Deepak Gupta
2024-08-20 19:45 ` Deepak Gupta
2024-08-20 22:33 ` Richard Henderson
2024-08-20 0:01 ` [PATCH v5 12/15] target/riscv: implement zicfiss instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 13/15] target/riscv: compressed encodings for sspush and sspopchk Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 14/15] disas/riscv: enable disassembly for zicfiss instructions Deepak Gupta
2024-08-20 0:01 ` [PATCH v5 15/15] disas/riscv: enable disassembly for compressed sspush/sspopchk Deepak Gupta
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