From: Richard Henderson <richard.henderson@linaro.org>
To: LIU Zhiwei <zhiwei_liu@linux.alibaba.com>, qemu-devel@nongnu.org
Cc: qemu-riscv@nongnu.org, palmer@dabbelt.com,
alistair.francis@wdc.com, dbarboza@ventanamicro.com,
liwei1518@gmail.com, bmeng.cn@gmail.com,
TANG Tiancheng <tangtiancheng.ttc@alibaba-inc.com>
Subject: Re: [PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes
Date: Mon, 2 Sep 2024 11:39:20 +1000 [thread overview]
Message-ID: <c0b4cb92-30fe-42dc-a245-57d3b3c04b82@linaro.org> (raw)
In-Reply-To: <20240830061607.1940-8-zhiwei_liu@linux.alibaba.com>
On 8/30/24 16:16, LIU Zhiwei wrote:
> From: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com>
>
> Signed-off-by: TANG Tiancheng<tangtiancheng.ttc@alibaba-inc.com>
> Reviewed-by: Liu Zhiwei<zhiwei_liu@linux.alibaba.com>
> ---
> tcg/riscv/tcg-target-con-set.h | 2 ++
> tcg/riscv/tcg-target-con-str.h | 1 +
> tcg/riscv/tcg-target.c.inc | 54 ++++++++++++++++++++++++++++++++++
> tcg/riscv/tcg-target.h | 2 +-
> 4 files changed, 58 insertions(+), 1 deletion(-)
>
> diff --git a/tcg/riscv/tcg-target-con-set.h b/tcg/riscv/tcg-target-con-set.h
> index d73a62b0f2..7277cb9af8 100644
> --- a/tcg/riscv/tcg-target-con-set.h
> +++ b/tcg/riscv/tcg-target-con-set.h
> @@ -22,4 +22,6 @@ C_N1_I2(r, r, rM)
> C_O1_I4(r, r, rI, rM, rM)
> C_O2_I4(r, r, rZ, rZ, rM, rM)
> C_O0_I2(v, r)
> +C_O0_I2(v, vK)
> C_O1_I1(v, r)
> +C_O1_I1(v, v)
> diff --git a/tcg/riscv/tcg-target-con-str.h b/tcg/riscv/tcg-target-con-str.h
> index 21c4a0a0e0..a4ae7b49c8 100644
> --- a/tcg/riscv/tcg-target-con-str.h
> +++ b/tcg/riscv/tcg-target-con-str.h
> @@ -17,6 +17,7 @@ REGS('v', GET_VREG_SET(riscv_vlen))
> */
> CONST('I', TCG_CT_CONST_S12)
> CONST('J', TCG_CT_CONST_J12)
> +CONST('K', TCG_CT_CONST_S5)
> CONST('N', TCG_CT_CONST_N12)
> CONST('M', TCG_CT_CONST_M12)
> CONST('Z', TCG_CT_CONST_ZERO)
> diff --git a/tcg/riscv/tcg-target.c.inc b/tcg/riscv/tcg-target.c.inc
> index b6b4bdc269..fde4e71260 100644
> --- a/tcg/riscv/tcg-target.c.inc
> +++ b/tcg/riscv/tcg-target.c.inc
> @@ -111,6 +111,7 @@ static TCGReg tcg_target_call_oarg_reg(TCGCallReturnKind kind, int slot)
> #define TCG_CT_CONST_N12 0x400
> #define TCG_CT_CONST_M12 0x800
> #define TCG_CT_CONST_J12 0x1000
> +#define TCG_CT_CONST_S5 0x2000
>
Added, but not used in this patch?
r~
next prev parent reply other threads:[~2024-09-02 1:39 UTC|newest]
Thread overview: 33+ messages / expand[flat|nested] mbox.gz Atom feed top
2024-08-30 6:15 [PATCH v2 00/14] tcg/riscv: Add support for vector LIU Zhiwei
2024-08-30 6:15 ` [PATCH v2 01/14] tcg/op-gvec: Fix iteration step in 32-bit operation LIU Zhiwei
2024-08-31 23:59 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 02/14] util: Add RISC-V vector extension probe in cpuinfo LIU Zhiwei
2024-09-02 0:12 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 03/14] tcg/riscv: Add basic support for vector LIU Zhiwei
2024-09-02 0:28 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 04/14] tcg/riscv: Add riscv vset{i}vli support LIU Zhiwei
2024-09-02 1:06 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 05/14] tcg/riscv: Implement vector load/store LIU Zhiwei
2024-09-02 1:31 ` Richard Henderson
2024-08-30 6:15 ` [PATCH v2 06/14] tcg/riscv: Implement vector mov/dup{m/i} LIU Zhiwei
2024-09-02 1:36 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 07/14] tcg/riscv: Add support for basic vector opcodes LIU Zhiwei
2024-09-02 1:39 ` Richard Henderson [this message]
2024-08-30 6:16 ` [PATCH v2 08/14] tcg/riscv: Implement vector cmp ops LIU Zhiwei
2024-09-03 6:45 ` Richard Henderson
2024-09-03 14:51 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 09/14] tcg/riscv: Implement vector neg ops LIU Zhiwei
2024-09-03 14:52 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 10/14] tcg/riscv: Implement vector sat/mul ops LIU Zhiwei
2024-09-03 14:52 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 11/14] tcg/riscv: Implement vector min/max ops LIU Zhiwei
2024-09-03 14:53 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 12/14] tcg/riscv: Implement vector shs/v ops LIU Zhiwei
2024-09-03 14:54 ` Richard Henderson
2024-08-30 6:16 ` [PATCH v2 13/14] tcg/riscv: Implement vector roti/v/x shi ops LIU Zhiwei
2024-09-03 15:15 ` Richard Henderson
2024-09-04 15:25 ` LIU Zhiwei
2024-09-04 19:05 ` Richard Henderson
2024-09-05 1:40 ` LIU Zhiwei
2024-08-30 6:16 ` [PATCH v2 14/14] tcg/riscv: Enable native vector support for TCG host LIU Zhiwei
2024-09-03 15:02 ` Richard Henderson
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