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charset=UTF-8; format=flowed Content-Transfer-Encoding: 8bit Received-SPF: pass client-ip=170.10.133.124; envelope-from=pbonzini@redhat.com; helo=us-smtp-delivery-124.mimecast.com X-Spam_score_int: -28 X-Spam_score: -2.9 X-Spam_bar: -- X-Spam_report: (-2.9 / 5.0 requ) BAYES_00=-1.9, DKIMWL_WL_HIGH=-0.84, DKIM_SIGNED=0.1, DKIM_VALID=-0.1, DKIM_VALID_AU=-0.1, DKIM_VALID_EF=-0.1, RCVD_IN_DNSWL_NONE=-0.0001, RCVD_IN_MSPIKE_H5=0.001, RCVD_IN_MSPIKE_WL=0.001, RCVD_IN_VALIDITY_CERTIFIED_BLOCKED=0.001, RCVD_IN_VALIDITY_RPBL_BLOCKED=0.001, SPF_HELO_NONE=0.001, SPF_PASS=-0.001 autolearn=ham autolearn_force=no X-Spam_action: no action X-BeenThere: qemu-devel@nongnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Errors-To: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org Sender: qemu-devel-bounces+qemu-devel=archiver.kernel.org@nongnu.org On 4/24/25 03:26, Alistair Francis wrote: > On Sun, Apr 6, 2025 at 5:03 PM Paolo Bonzini wrote: >> >> This is the combination of the previously posted series to store max SATP >> mode in RISCVCPUConfig as a single integer, and convert CPU definitions >> to a small extension of RISCVCPUConfig called RISCVCPUDef. I put them >> together because the first part (patches 1-6) is already acked/reviewed. >> >> As mentioned in the earlier submissions, the main reason for me to do this >> is to remove .instance_post_init, which RISC-V is using in a slightly different >> way than everyone else. Whereas other uses (including x86, which is >> currently buggy, and Rust) would prefer to call .instance_post_init >> from root to leaf, RISC-V needs it to be called from leaf (CPU model) >> to parent (DeviceState). The fix is to move the logic of the former >> .instance_post_init callback for the leaf at the end of the leaf's >> .instance_init, as done in this series. >> >> Paolo >> >> Supersedes: <20250228102747.867770-1-pbonzini@redhat.com> >> >> Paolo Bonzini (27): >> hw/riscv: acpi: only create RHCT MMU entry for supported types >> target/riscv: assert argument to set_satp_mode_max_supported is valid >> target/riscv: cpu: store max SATP mode as a single integer >> target/riscv: update max_satp_mode based on QOM properties >> target/riscv: remove supported from RISCVSATPMap >> target/riscv: move satp_mode.{map,init} out of CPUConfig >> target/riscv: introduce RISCVCPUDef >> target/riscv: store RISCVCPUDef struct directly in the class >> target/riscv: merge riscv_cpu_class_init with the class_base function >> target/riscv: move RISCVCPUConfig fields to a header file >> target/riscv: include default value in cpu_cfg_fields.h.inc >> target/riscv: do not make RISCVCPUConfig fields conditional >> target/riscv: add more RISCVCPUDef fields >> target/riscv: convert abstract CPU classes to RISCVCPUDef >> target/riscv: convert profile CPU models to RISCVCPUDef >> target/riscv: convert bare CPU models to RISCVCPUDef >> target/riscv: convert dynamic CPU models to RISCVCPUDef >> target/riscv: convert SiFive E CPU models to RISCVCPUDef >> target/riscv: convert ibex CPU models to RISCVCPUDef >> target/riscv: convert SiFive U models to RISCVCPUDef >> target/riscv: th: make CSR insertion test a bit more intuitive >> target/riscv: generalize custom CSR functionality >> target/riscv: convert TT C906 to RISCVCPUDef >> target/riscv: convert TT Ascalon to RISCVCPUDef >> target/riscv: convert Ventana V1 to RISCVCPUDef >> target/riscv: convert Xiangshan Nanhu to RISCVCPUDef >> target/riscv: remove .instance_post_init > > Thanks! > > Applied to riscv-to-apply.next > > Alistair As Daniel noticed, I was expecting https://lore.kernel.org/qemu-devel/20250210133134.90879-1-philmd@linaro.org/ to get in before this series. If you need a version that applies without that series, you can pull from branch riscv-for-alistair of https://github.com/bonzini/qemu. Paolo