From mboxrd@z Thu Jan 1 00:00:00 1970 Received: from eggs.gnu.org ([2001:4830:134:3::10]:55332) by lists.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1boUuo-0006GQ-Jq for qemu-devel@nongnu.org; Mon, 26 Sep 2016 08:21:50 -0400 Received: from Debian-exim by eggs.gnu.org with spam-scanned (Exim 4.71) (envelope-from ) id 1boUuk-000861-6J for qemu-devel@nongnu.org; Mon, 26 Sep 2016 08:21:46 -0400 Received: from mail-wm0-f65.google.com ([74.125.82.65]:35516) by eggs.gnu.org with esmtp (Exim 4.71) (envelope-from ) id 1boUuj-00085r-W2 for qemu-devel@nongnu.org; Mon, 26 Sep 2016 08:21:42 -0400 Received: by mail-wm0-f65.google.com with SMTP id 133so13845090wmq.2 for ; Mon, 26 Sep 2016 05:21:41 -0700 (PDT) Sender: Paolo Bonzini References: From: Paolo Bonzini Message-ID: Date: Mon, 26 Sep 2016 14:20:39 +0200 MIME-Version: 1.0 In-Reply-To: Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Subject: Re: [Qemu-devel] [PATCH 00/18] target-riscv: Add full-system emulation support for the RISC-V Instruction Set Architecture (RV64G, RV32G) List-Id: List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , To: Sagar Karandikar , qemu-devel@nongnu.org Cc: peter.maydell@linaro.org, kbastian@mail.uni-paderborn.de, rth@twiddle.net On 26/09/2016 12:56, Sagar Karandikar wrote: > -cpu-qom.h merged into cpu.h Please follow the model of other targets. RISCVCPUClass and the RISCVCPU typedef should be in cpu-qom.h. Paolo